10AS048K4F35E3SG datasheet, PDF

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10AS048K4F35E3SG: DescriptionFPGA - Field Programmable Gate Array Arria 10 SX 480 SoC FPGA; CategoryProgrammable logic devices Programmable logic; File Size384KB，42 Pages; ManufacturerAltera (Intel); Environmental Compliance

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10AS048K4F35E3SG Overview

FPGA - Field Programmable Gate Array Arria 10 SX 480 SoC FPGA

10AS048K4F35E3SG Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Altera (Intel)
package instruction	BGA, BGA1152,34X34,40
Reach Compliance Code	compliant
JESD-30 code	S-PBGA-B1152
length	35 mm
Number of entries	396
Number of logical units	480000
Output times	396
Number of terminals	1152
Maximum operating temperature	100 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA1152,34X34,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	0.9 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	3.5 mm
Maximum supply voltage	0.93 V
Minimum supply voltage	0.87 V
Nominal supply voltage	0.9 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	35 mm

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Intel

Arria

10 Device Overview

A10-OVERVIEW

2017.09.20

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Contents

Intel

Arria

10 Device Overview....................................................................................... 3

Key Advantages of Intel Arria 10 Devices........................................................................ 4

Summary of Intel Arria 10 Features................................................................................ 4

Intel Arria 10 Device Variants and Packages.....................................................................7

Intel Arria 10 GX.................................................................................................7

Intel Arria 10 GT............................................................................................... 11

Intel Arria 10 SX............................................................................................... 14

I/O Vertical Migration for Intel Arria 10 Devices.............................................................. 17

Adaptive Logic Module................................................................................................ 17

Variable-Precision DSP Block........................................................................................18

Embedded Memory Blocks........................................................................................... 20

Types of Embedded Memory............................................................................... 21

Embedded Memory Capacity in Intel Arria 10 Devices............................................ 21

Embedded Memory Configurations for Single-port Mode......................................... 22

Clock Networks and PLL Clock Sources.......................................................................... 22

Clock Networks................................................................................................. 22

Fractional Synthesis and I/O PLLs........................................................................22

FPGA General Purpose I/O........................................................................................... 23

External Memory Interface.......................................................................................... 24

Memory Standards Supported by Intel Arria 10 Devices......................................... 24

PCIe Gen1, Gen2, and Gen3 Hard IP............................................................................. 26

Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet............................................. 26

Interlaken Support............................................................................................ 26

10 Gbps Ethernet Support.................................................................................. 26

Low Power Serial Transceivers......................................................................................27

Transceiver Channels......................................................................................... 28

PMA Features................................................................................................... 29

PCS Features.................................................................................................... 30

SoC with Hard Processor System.................................................................................. 32

Key Advantages of 20-nm HPS............................................................................33

Features of the HPS...........................................................................................35

FPGA Configuration and HPS Booting................................................................... 37

Hardware and Software Development.................................................................. 37

Dynamic and Partial Reconfiguration............................................................................. 37

Dynamic Reconfiguration....................................................................................37

Partial Reconfiguration....................................................................................... 37

Enhanced Configuration and Configuration via Protocol.................................................... 38

SEU Error Detection and Correction.............................................................................. 39

Power Management.................................................................................................... 39

Incremental Compilation............................................................................................. 40

Document Revision History.......................................................................................... 40

Intel

Arria

10 Device Overview

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