PI6C49015
Embedded Clock Generator
Features
Î
Î
Î
Description
The PI6C49015 is a high performance networking clock
generator which generates
PCIe 2.0 Compliant
100MHz HCSL
clock signals along with two LVCMOS 25MHz clock from either
25MHz crystal or reference input. This integrated solution is
ideal for Networking, Embedded systems and other systems that
require
PCIe 1.0 and 2.0
HCSL signals and 25MHz clocks yet
small foot print.
3.3V
±10%
supply voltage
25MHz XTAL or reference clock input
Five PCIe® 2.0 Compliant 100MHz selectable HCSL outputs
with -0.5% spread
– default is spread off
Two 25MHz LVCMOS output
Industrial temperature range: -40°C to 85°C
Packaging (Pb free and Green)
à
TSSOP 28 (L)
Î
Î
Î
Applications
Î
Î
Î
Networking systems
Embedded systems
Other systems
Block Diagram
Pin Configuration
IREF
100M_Q4-
100M_Q4+
100MHz
5
O
GND0_100M
100M_Q0-
100M_Q0+
100M_Q1+
100M_Q1-
VDDA
GNDA
VDDO_100M
VDDO_100M
GNDO_100M
100M_Q2+
100M_Q2-
VDD_XTAL
X2
X1/REFIN
X2
Crystal
Ocillator
PLL Clock Synthesis
& Spread Spectrum
& Control Circuit
100M_Q3-
100M_Q3+
SCLK
SDATA
GND_25M
25M_OUT1
25M_OUT2
VDD_25M
GND_XTAL
PDRESET
X1
Q_25M
2
SCLK
SDATA
475 Ohm
IREF
12-0168
1
www.pericom.com
P-0.1
02/29/12
Embedded Clock Generator
Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Pin Name
IREF
100M_Q4-
100M_Q4+
100M_Q3-
100M_Q3+
SCLK
SDATA
GND_25M
25M_OUT1
25M_OUT2
VDD_25M
GND_XTAL
PDRESET
X1
X2
VDD_XTAL
100M_Q2-
100M_Q2+
GNDO_100M
VDDO_100M
VDDO_100M
GNDA
VDDA
100M_Q1-
100M_Q1+
100M_Q0+
100M_Q0-
GNDO_100M
Pin Type
Output
Output
Output
Output
Output
Input
I/O
Power
Output
Output
Power
Power
Input
Input
Output
Power
Output
Output
Output
Power
Power
Power
Power
Output
Output
Output
Output
Power
Pin Description
Connect to 475-Ohm resistor to set HCSL output drive current
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
SMBus compatible input clock. Supports fast mode 400 kHz input clock
SMBus compatible data line
Ground for 25MHz output
25MHz LVCMOS output. When disabled, output is trisated and has a normal
110kOhm pull-down
25MHz LVCMOS output. When disabled, output is trisated and has a normal
110kOhm pull-down
3.3V supply for 25MHz output
Ground for XTAL
Power on reset, when low all PLLs are powered down and output trisated. SMBus
registers are reset to default values
Crystal input. Integrated 6pf capacitance
Crystal output. Integrated 6pf capacitance
3.3V supply for XTAL
100MHz HCSL output
100MHz HCSL output
Ground for 100MHz output buffer
3.3V supply for 100MHz output buffer
3.3V supply for 100MHz output buffer
Ground for 100MHz related PLL
3.3V supply for 100MHz related PLL
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
Ground for 100MHz output buffer
PI6C49015
12-0168
2
www.pericom.com
P-0.1
02/29/12
Embedded Clock Generator
Serial Data Interface (SMBus)
PI6C49015 is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit ad-
dress and read/write bit as shown below.
Address Assignment
PI6C49015
A6
1
How to Write
1 bit
Start
bit
Note:
1.
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
0/1
8 bits
d2H
1
Ack
8 bits
Register
offset
1
Ack
8 bits
Byte
Count = N
1
Ack
8 bits
Data Byte
0
1
Ack
…
8 bits
Data Byte
N-1
1
Ack
1 bit
Stop
bit
Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
How to Read
(M: abbreviation for Master or Controller; S: abbreviation for slave/clock)
1 bit
8
bits
1 bit
8
bits
M:
send
start-
ing
data-
byte
loca-
tion:
N
1 bit
1 bit
8
bits
1 bit
8
bits
S:
sends
# of
data
bytes
that
will
be
sent:
X
1 bit
8
bits
S:
sends
start-
ing
data
byte
N
1 bit
…
8
bits
S:
sends
data
byte
N+X-
1
1 bit
1 bit
M:
Start
bit
M:
Send
"D2h"
S:
sends
Ack
S:
sends
Ack
M:
Start
bit
M:
Send
"D3h"
S:
sends
Ack
M:
sends
Ack
M:
sends
Ack
…
M: Not
Ac-
knowl-
edge
M:
Stop
bit
Byte 0: Spread Spectrum Control Register
Bit
7
6
5
4 to 1
0
Description
Spread Spectrum Selection for 100 MHz HCSL
PCI-Express clocks
Enables hardware or software control of OE bits
(see Byte 0–Bit 6 and Bit 5 Functionality table)
Software PD_RESET bit. Enables or disables all
outputs
(see Byte 0–Bit 6 and Bit 5 Functionality table)
Reserved
OE for 25M_Out2
Type
RW
RW
RW
RW
RW
Power Up
Condition
0
0
1
Undefined
1
Output(s)
Affected
All 100MHz HCSL
PCI Express output
PD_RESET pin,
bit 5
All outputs
Not Applicable
25M_Out2
0 = disabled
1 = enabled
Notes
0=spread off
1 = -0.5% down
spread
0 = hardware cntl
1 = software ctrl
0 = disabled
1 = enabled
12-0168
3
www.pericom.com
P-0.1
02/29/12
Embedded Clock Generator
Byte 0 - Bit 6 and Bit 5 Functionality
Bit 6
0
1
1
Bit 5
X
0
1
Description
PD_RESET HW pin/signal = enabled
Disables all outputs and tri-states the outputs, PD_RESET HW pin/signal = DO NOT CARE
Enable all outputs, PD_RESET HW pin/signal = DON'T CARE
PI6C49015
Byte 1: Control Register
Bit
7
6
5
4
3
2
1 to 0
Description
Reserved
OE for 25M_Out1
Reserved
OE for 100M_Q4 HCSL output
Reserved
OE for 100M_Q3 HCSL output
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
Power Up Con-
dition
Undefined
1
Undefined
1
Undefined
1
Undefined
Output(s) Affected
Not Applicable
25M_Out1
Not Applicable
100M_Q4
Not Applicable
100M_Q3
Not Applicable
Notes
0 = disabled
1 = enabled
0=disable
1 = enabled
0=disable
1 = enabled
Byte 2: Control Register
Bit
7 to 5
4 to 0
Description
Reserved
Reserved
Type
RW
R
Power Up Condi-
Output(s) Affected
tion
Undefined
Undefined
Not Applicable
Not Applicable
Notes
12-0168
4
www.pericom.com
P-0.1
02/29/12
Embedded Clock Generator
Byte 3: Control Register
Bit
7
6 to 3
2
1
0
PI6C49015
Description
OE for 100M_Q2 HCSL Output
Reserved
OE for 100M_Q1 HCSL Output
OE for 100M_Q0 HCSL Output
Reserved
Type
RW
RW
RW
RW
R
Power Up
Condition
1
Undefined
1
1
Undefined
Output(s) Affected
100M_Q2
Not Applicable
100M_Q1
100M_Q0
Not Applicable
Notes
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
Byte 4 & 5: Control Register
Bit
7 to 0
Description
Reserved
Type
R
Power Up Con-
dition
Undefined
Output(s) Affected
Not Applicable
Notes
Byte 6: Control Register
Bit
7
6
5
4
3
2
1
0
Description
Revision ID bit 3
Revision ID bit 2
Revision ID bit 1
Revision ID bit 0
Vendor ID bit 3
Vendor ID bit 2
Vendor ID bit 1
Vendor ID bit 0
Type
R
R
R
R
R
R
R
R
Power Up Con-
dition
1
0
0
0
0
0
1
1
Output(s) Affected
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Notes
12-0168
5
www.pericom.com
P-0.1
02/29/12
京公网安备 11010802033920号
EEWORLD
