and/or fractional divides are allowed on two of the PLLs.
There are a total of five 8-bit output dividers. Each output
bank can be configured to support LVTTL, LVPECL, LVDS
or HCSL logic levels. Out0 (Output 0) supports 3.3V
single-ended output only. The outputs are connected to the
PLLs via a switch matrix. The switch matrix allows the user
to route the PLL outputs to any output bank. This feature
can be used to simplify and optimize the board layout. In
addition, each output's slew rate and enable/disable
function is programmable.
IDT5V49EE701
Features
•
•
•
•
•
•
Four internal PLLs
Internal non-volatile EEPROM
Fast (400kHz) mode I
2
C serial interface
Input frequency range: 1 MHz to 200 MHz
Output frequency range: 4.9 kHz to 500 MHz
Reference crystal input with programmable linear load
capacitance
– Crystal frequency range: 8 MHz to 50 MHz
•
Each PLL has a 7-bit reference divider and a 12-bit
feedback-divider
•
8-bit output-divider blocks
•
Fractional division capability on one PLL
•
Two of the PLLs support spread spectrum generation
capability
•
I/O Standards:
– Outputs - 3.3 V LVTTL/ LVCMOS
– Outputs - LVPECL, LVDS and HCSL
– Inputs - 3.3 V LVTTL/ LVCMOS
•
•
•
•
•
•
•
•
•
Programmable slew rate control
Programmable loop bandwidth
Programmable output inversion to reduce bimodal jitter
Redundant clock inputs with auto and manual switchover
options
Individual output enable/disable
Power-down mode
3.3V core V
DD
Available in VFQFPN package
-40 to +85 C Industrial Temp operation
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR
1
IDT5V49EE701
REV P 071015
IDT5V49EE701
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
Functional Block Diagram
S
R
C
0
S
R
C
1
S
R
C
2
S1
OUT0
XIN/REF
XOUT
PLL0 (SS)
/DIV1
OUT1
CLKIN
PLL1
/DIV2
OUT2
CLKSEL
PLL2
PLL3 (SS)
S
R
C
3
S
R
C
6
S3
/DIV3
OUT3
SD/OE
SDA
SCL
SEL[2:0]
Control
Logic
/DIV6
OUT6
S
R
C
5
OUT5
/DIV5
OUT5
1. OUT1 & OUT2, OUT3 & OUT6, and OUT5 & OUT5 pairs can be configured to be
LVDS, LVPECL or HCSL, or two single-ended LVTTL outputs.
2. CLKIN, CLKSEL, SD/OE and SEL[2:0] have pull down resistors.
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR
2
IDT5V49EE701
REV P 071015
IDT5V49EE701
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
Pin Configuration
SD/OE
OUT0
SEL2
SEL1
SEL0
GND
VDD
VDD
XOUT
XIN/REF
VDDx
CLKIN
GND
OUT1
1
2
3
4
5
6
7
28 27 26 25 24 23 22
21
20
19
18
17
16
15
8
OUT2
9 10 11 12 13 14
OUT5
OUT5b
GND
VDD
VDD
GND
OUT3
OUT6
GND
AVDD
CLKSEL
SCLK
SDAT
28 pin VFQFPN
(Top View)
Pin Descriptions
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
Pin Name
VDD
XOUT
XIN / REF
I/O
O
I
Pin Type
Power
LVTTL
LVTTL
Power
Pin Description
Device power supply. Connect to 3.3V.
CRYSTAL_OUT -- Reference crystal feedback.
CRYSTAL_IN -- Reference crystal input or external
reference clock input.
Crystal oscillator power supply. Connect to 3.3V through
5 resistor. Use filtered analog power supply if available.
Input clock. Weak internal pull down resistor.
Connect to Ground.
Configurable clock output 1. Single-ended or differential
when combined with OUT2.
Configurable clock output 2. Single-ended or differential
when combined with OUT1.
Device power supply. Connect to 3.3V.
Connect to Ground.
Configurable clock output 5. Single-ended or differential
when combined with OUT5b.
Configurable clock output 5b. Single-ended or differential
when combined with OUT5.
VDDx
CLKIN
GND
OUT1
OUT2
VDD
GND
OUT5
OUT5b
O
O
O
O
I
LVTTL
Power
Adjustable
1
Adjustable
1
Power
Power
Adjustable
1,2
Adjustable
1,2
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR
3
IDT5V49EE701
REV P 071015
IDT5V49EE701
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
Pin#
13
14
15
Pin Name
VDD
GND
SDAT
I/O
Pin Type
Power
Power
Pin Description
Device power supply. Connect to 3.3V.
Connect to Ground.
Bidirectional I
2
C data. An external pull-up resistor is
required. See I
2
C specification for pull-up value
recommendation.
I
2
C clock. An external pull-up resistor is required. See
I
2
C specification for pull-up value recommendation.
Input clock selector. Weak internal pull down resistor.
Device analog power supply. Connect to 3.3V. Use
filtered analog power supply if available.
Connect to Ground.
Configurable clock output 6. Single-ended or differential
when combined with OUT3.
Configurable clock output 3. Single-ended or differential
when combined with OUT6.
Device power supply. Connect to 3.3V.
Configuration select pin. Weak internal pull down
resistor.
Configuration select pin. Weak internal pull down
resistor.
Configuration select pin. Weak internal pull down
resistor.
Enables/disables the outputs or powers down the chip.
The SP bit (0x02) controls the polarity of the signal to be
either active HIGH or LOW. (Default is active LOW.)
Weak internal pull down resistor.
Configurable clock output 0.
Connect to Ground.
I/O
Open Drain
16
17
18
19
20
21
22
23
24
25
26
SCLK
CLKSEL
AVDD
GND
OUT6
OUT3
VDD
SEL2
SEL1
SEL0
SD/OE
I
I
LVTTL
LVTTL
Power
Power
O
O
Adjustable
1
Adjustable
1
Power
I
I
I
I
LVTTL
LVTTL
LVTTL
LVTTL
27
28
OUT0
GND
O
LVTTL
Power
1.Outputs are user programmable to drive single-ended 3.3-V LVTTL, or differential LVDS, LVPECL or HCSL interface levels
2. When only an individual single-ended clock output is required, tie OUT# and OUT#b together.
3. Analog power plane should be isolated from a 3.3V power plane through a ferrite bead.
4. Each power pin should have a dedicated 0.01µF de-coupling capacitor. Digital VDDs may be tied together.
5. Unused clock inputs (REFIN or CLKIN) must be pulled high or low - they cannot be left floating. If the crystal oscillator is not used, XOUT must be left floating.
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR
4
IDT5V49EE701
REV P 071015
IDT5V49EE701
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
PLL Features and Descriptions
7-bit
D
VCO
4-bit
A
12-bit
N
Sigm a-Delta
M odulator
PLL0 Block Diagram
7-bit
D
VCO
12-bit
N
PLL1, PLL2 and PLL3 Block Diagram
Pre-Divider
(D)
1
Values
PLL0
PLL1
PLL2
PLL3
1 - 127
1 - 127
1 - 127
3 - 127
Multiplier
(M)
2
Values
10 - 8206
1 - 4095
1 - 4095
12 - 4095
Programmable
Spread Spectrum
Loop Bandwidth Generation Capability
Yes
Yes
Yes
Yes
Yes
No
No
Yes
1.For PLL0, PLL1 and PLL2, D=0 means PLL power down. For PLL3, 0, 1, and 2 are DNU (do not use)
2.For PLL0, M = 2*N + A + 1 (for A > 0); M = 2*N (for A = 0); A < N-1. For PLL1, PLL2 and PLL3, M=N.
京公网安备 11010802033920号
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