C8051F55x/56x/57x
Mixed Signal ISP Flash MCU Family
Analog Peripherals
-
12-Bit ADC
•
•
•
•
•
Up to 200 ksps
Up to 32 external single-ended inputs
VREF from on-chip VREF, external pin or V
DD
Internal or external start of conversion source
Built-in temperature sensor
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current
Memory
-
2304 bytes internal data RAM (256 + 2048 XRAM)
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32 or 16 kB Flash; In-system programmable in
512-byte Sectors
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Two Comparators
•
•
•
Digital Peripherals
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33, 25, or 18 Port I/O; All 5 V tolerant
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CAN 2.0 Controller—no crystal required
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LIN 2.1 Controller (Master and Slave capable); no
-
-
-
crystal required
Hardware enhanced UART, SMBus™, and
enhanced SPI™ serial ports
Four general purpose 16-bit counter/timers
16-bit programmable counter array (PCA) with six
capture/compare modules and enhanced PWM
functionality
On-Chip Debug
-
On-chip debug circuitry facilitates full speed, non-
-
-
intrusive in-system debug (no emulator required)
Provides breakpoints, single stepping,
inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
Low cost, complete development kit
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Supply Voltage 1.8 to 5.25 V
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Typical operating current: 19 mA at 50 MHz
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Typical stop mode current: 1 µA
High-Speed 8051 µC Core
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Pipelined instruction architecture; executes 70% of
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-
instructions in 1 or 2 system clocks
Up to 50 MIPS throughput with 50 MHz clock
Expanded interrupt handler
Clock Sources
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Internal 24 MHz with ±0.5% accuracy for CAN and
-
-
master LIN operation
External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
Can switch between clock sources on-the-fly;
useful in power saving modes
Packages
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40-pin QFN (C8051F568-9 and ‘F570-5)
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32-pin QFP/QFN (C8051F560-7)
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24-pin QFN (C8051F550-7)
Automotive Qualified
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Temperature Range: –40 to +125 °C
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Compliant to AEC-Q100
ANALOG
PERIPHERALS
A
M
U
X
DIGITAL I/O
UART 0
SMBus
SPI
PCA
Timers 0-3
CAN
LIN
Ports 0-4
Crossbar
External
Memory
Interface
12-bit
200 ksps
ADC
TEMP
SENSOR
VREG
Voltage
Comparators 0-1 VREF
24 MHz PRECISION
INTERNAL OSCILLATOR
2x Clock Multiplier
HIGH-SPEED CONTROLLER CORE
32 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(50 MIPS)
DEBUG
CIRCUITRY
2 kB XRAM
POR
WDT
Rev. 1.2 9/14
Copyright © 2014 by Silicon Laboratories
C8051F55x, C8051F56x, C8051F57x
C8051F55x/56x/57x
2
Rev. 1.2
C8051F55x/56x/57x
Table of Contents
1. System Overview ..................................................................................................... 16
2. Ordering Information ............................................................................................... 20
3. Pin Definitions.......................................................................................................... 22
4. Package Specifications ........................................................................................... 28
4.1. QFN-40 Package Specifications........................................................................ 28
4.2. QFP-32 Package Specifications........................................................................ 30
4.3. QFN-32 Package Specifications........................................................................ 32
4.4. QFN-24 Package Specifications........................................................................ 34
5. Electrical Characteristics ........................................................................................ 36
5.1. Absolute Maximum Specifications..................................................................... 36
5.2. Electrical Characteristics ................................................................................... 37
6. 12-Bit ADC (ADC0) ................................................................................................... 47
6.1. Modes of Operation ........................................................................................... 48
6.1.1. Starting a Conversion................................................................................ 48
6.1.2. Tracking Modes......................................................................................... 48
6.1.3. Timing ....................................................................................................... 49
6.1.4. Burst Mode................................................................................................ 50
6.2. Output Code Formatting .................................................................................... 52
6.2.1. Settling Time Requirements...................................................................... 52
6.3. Selectable Gain ................................................................................................. 53
6.3.1. Calculating the Gain Value........................................................................ 53
6.3.2. Setting the Gain Value .............................................................................. 55
6.4. Programmable Window Detector....................................................................... 61
6.4.1. Window Detector In Single-Ended Mode .................................................. 63
6.5. ADC0 Analog Multiplexer .................................................................................. 65
6.6. Temperature Sensor.......................................................................................... 67
7. Voltage Reference.................................................................................................... 68
8. Comparators............................................................................................................. 70
8.1. Comparator Multiplexer ..................................................................................... 76
9. Voltage Regulator (REG0) ....................................................................................... 79
10. CIP-51 Microcontroller........................................................................................... 81
10.1. Performance .................................................................................................... 81
10.2. Instruction Set.................................................................................................. 83
10.2.1. Instruction and CPU Timing .................................................................... 83
10.3. CIP-51 Register Descriptions .......................................................................... 87
10.4. Serial Number Special Function Registers (SFRs) ......................................... 91
11. Memory Organization ............................................................................................ 92
11.1. Program Memory............................................................................................. 92
11.1.1. MOVX Instruction and Program Memory ................................................ 93
11.2. Data Memory ................................................................................................... 93
11.2.1. Internal RAM ........................................................................................... 93
12. Special Function Registers................................................................................... 95
12.1. SFR Paging ..................................................................................................... 95
Rev. 1.2
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C8051F55x/56x/57x
12.2. Interrupts and SFR Paging .............................................................................. 95
12.3. SFR Page Stack Example ............................................................................... 97
13. Interrupts .............................................................................................................. 112
13.1. MCU Interrupt Sources and Vectors.............................................................. 112
13.1.1. Interrupt Priorities.................................................................................. 113
13.1.2. Interrupt Latency ................................................................................... 113
13.2. Interrupt Register Descriptions ...................................................................... 115
13.3. External Interrupts INT0 and INT1................................................................. 122
14. Flash Memory....................................................................................................... 124
14.1. Programming The Flash Memory .................................................................. 124
14.1.1. Flash Lock and Key Functions .............................................................. 124
14.1.2. Flash Erase Procedure ......................................................................... 125
14.1.3. Flash Write Procedure .......................................................................... 125
14.1.4. Flash Write Optimization ....................................................................... 126
14.2. Non-volatile Data Storage ............................................................................. 127
14.3. Security Options ............................................................................................ 127
14.4. Flash Write and Erase Guidelines ................................................................. 129
14.4.1. V
DD
Maintenance and the V
DD
monitor ................................................ 129
14.4.2. PSWE Maintenance .............................................................................. 130
14.4.3. System Clock ........................................................................................ 130
15. Power Management Modes................................................................................. 135
15.1. Idle Mode....................................................................................................... 135
15.2. Stop Mode ..................................................................................................... 136
15.3. Suspend Mode .............................................................................................. 136
16. Reset Sources ...................................................................................................... 138
16.1. Power-On Reset ............................................................................................ 139
16.2. Power-Fail Reset/VDD Monitor ..................................................................... 139
16.3. External Reset ............................................................................................... 141
16.4. Missing Clock Detector Reset ....................................................................... 141
16.5. Comparator0 Reset ....................................................................................... 142
16.6. PCA Watchdog Timer Reset ......................................................................... 142
16.7. Flash Error Reset .......................................................................................... 142
16.8. Software Reset .............................................................................................. 142
17. External Data Memory Interface and On-Chip XRAM ....................................... 144
17.1. Accessing XRAM........................................................................................... 144
17.1.1. 16-Bit MOVX Example .......................................................................... 144
17.1.2. 8-Bit MOVX Example ............................................................................ 144
17.2. Configuring the External Memory Interface ................................................... 145
17.3. Port Configuration.......................................................................................... 145
17.4. Multiplexed Mode .......................................................................................... 149
17.5. Memory Mode Selection................................................................................ 150
17.5.1. Internal XRAM Only .............................................................................. 150
17.5.2. Split Mode without Bank Select............................................................. 150
17.5.3. Split Mode with Bank Select.................................................................. 151
17.5.4. External Only......................................................................................... 151
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C8051F55x/56x/57x
17.6. Timing .......................................................................................................... 151
17.6.1. Multiplexed Mode .................................................................................. 153
18. Oscillators and Clock Selection ......................................................................... 157
18.1. System Clock Selection................................................................................. 157
18.2. Programmable Internal Oscillator .................................................................. 159
18.2.1. Internal Oscillator Suspend Mode ......................................................... 159
18.3. Clock Multiplier .............................................................................................. 162
18.4. External Oscillator Drive Circuit..................................................................... 164
18.4.1. External Crystal Example...................................................................... 166
18.4.2. External RC Example............................................................................ 167
18.4.3. External Capacitor Example.................................................................. 167
19. Port Input/Output ................................................................................................. 169
19.1. Port I/O Modes of Operation.......................................................................... 170
19.1.1. Port Pins Configured for Analog I/O...................................................... 170
19.1.2. Port Pins Configured For Digital I/O...................................................... 170
19.1.3. Interfacing Port I/O in a Multi-Voltage System ...................................... 171
19.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 171
19.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 171
19.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 171
19.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions ... 172
19.3. Priority Crossbar Decoder ............................................................................. 172
19.4. Port I/O Initialization ...................................................................................... 174
19.5. Port Match ..................................................................................................... 179
19.6. Special Function Registers for Accessing and Configuring Port I/O ............. 183
20. Local Interconnect Network (LIN0)..................................................................... 193
20.1. Software Interface with the LIN Controller..................................................... 194
20.2. LIN Interface Setup and Operation................................................................ 194
20.2.1. Mode Definition ..................................................................................... 194
20.2.2. Baud Rate Options: Manual or Autobaud ............................................. 194
20.2.3. Baud Rate Calculations: Manual Mode................................................. 194
20.2.4. Baud Rate Calculations—Automatic Mode ........................................... 196
20.3. LIN Master Mode Operation .......................................................................... 197
20.4. LIN Slave Mode Operation ............................................................................ 198
20.5. Sleep Mode and Wake-Up ............................................................................ 199
20.6. Error Detection and Handling ........................................................................ 199
20.7. LIN Registers................................................................................................. 200
20.7.1. LIN Direct Access SFR Registers Definitions ....................................... 200
20.7.2. LIN Indirect Access SFR Registers Definitions ..................................... 202
21. Controller Area Network (CAN0) ........................................................................ 210
21.1. Bosch CAN Controller Operation................................................................... 211
21.1.1. CAN Controller Timing .......................................................................... 211
21.1.2. CAN Register Access............................................................................ 212
21.1.3. Example Timing Calculation for 1 Mbit/Sec Communication ................ 212
21.2. CAN Registers............................................................................................... 214
21.2.1. CAN Controller Protocol Registers........................................................ 214
Rev. 1.2
5
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