MC14046B
Phase Locked Loop
The MC14046B phase locked loop contains two phase comparators,
a voltage−controlled oscillator (VCO), source follower, and zener
diode. The comparators have two common signal inputs, PCA
in
and
PCB
in
. Input PCA
in
can be used directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to small voltage
signals. The self−bias circuit adjusts small voltage signals in the linear
region of the amplifier. Phase comparator 1 (an exclusive OR gate)
provides a digital error signal PC1
out
, and maintains 90° phase shift at
the center frequency between PCA
in
and PCB
in
signals (both at 50%
duty cycle). Phase comparator 2 (with leading edge sensing logic)
provides digital error signals, PC2
out
and LD, and maintains a 0°
phase shift between PCA
in
and PCB
in
signals (duty cycle is
immaterial). The linear VCO produces an output signal VCO
out
whose frequency is determined by the voltage of input VCO
in
and the
capacitor and resistors connected to pins C1
A
, C1
B
, R1, and R2.
The source−follower output SF
out
with an external resistor is used
where the VCO
in
signal is needed but no loading can be tolerated.
The inhibit input Inh, when high, disables the VCO and source
follower to minimize standby power consumption. The zener diode
can be used to assist in power supply regulation.
Applications include FM and FSK modulation and demodulation,
frequency synthesis and multiplication, frequency discrimination,
tone decoding, data synchronization and conditioning,
voltage−to−frequency conversion and motor speed control.
Features
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SOIC−16 WB
DW SUFFIX
CASE 751G
SOEIAJ−16
F SUFFIX
CASE 966
MARKING DIAGRAMS
16
14046BG
AWLYYWW
1
SOIC−16 WB
A
WL, L
YY, Y
WW, W
G
1
SOEIAJ−16
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
16
MC14046B
ALYWG
•
•
•
•
•
Buffered Outputs Compatible with Low−Power TTL
Diode Protection on All Inputs
Supply Voltage Range = 3.0 to 18 V
Pin−for−Pin Replacement for CD4046B
Phase Comparator 1 is an Exclusive OR Gate and is Duty Cycle
Limited
•
Phase Comparator 2 Switches on Rising Edges and is not Duty Cycle
Limited
•
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•
These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Symbol
V
DD
V
in
I
in
P
D
T
A
T
stg
DC Supply Voltage Range
Input Voltage Range (All Inputs)
DC Input Current, per Pin
Power Dissipation, per Package (Note 1)
Operating Temperature Range
Storage Temperature Range
Parameter
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
This device contains protection circuitry to guard
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid ap-
plications of any voltage higher than maximum rated
voltages to this high−impedance circuit. For proper op-
eration, V
in
and V
out
should be constrained to the range
V
SS
≤
(V
in
or V
out
)
≤
V
DD
.
Unused inputs must always be tied to an appropriate
logic voltage level (e.g., either V
SS
or V
DD
). Unused out-
puts must be left open.
Value
−0.5 to +18.0
−0.5 to V
DD
+ 0.5
±
10
500
−55 to +125
−65 to +150
Unit
V
V
mA
mW
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
©
Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 14
Publication Order Number:
MC14046B/D
MC14046B
BLOCK DIAGRAM
PCA
in
14
PCB
in
3
VCO
in
9
V
DD
= PIN 16
V
SS
= PIN 8
INH 5
V
SS
SELF BIAS
CIRCUIT
PHASE
COMPARATOR 1
PHASE
COMPARATOR 2
VOLTAGE
CONTROLLED
OSCILLATOR
(VCO)
SOURCE FOLLOWER
2 PC1
out
13 PC2
out
1 LD
4
11
12
6
7
VCO
out
R1
R2
C1
A
C1
B
PIN ASSIGNMENT
LD
PC1
out
PCB
in
VCO
out
INH
C1
A
C1
B
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
ZENER
PCA
in
PC2
out
R2
R1
SF
out
VCO
in
10 SF
out
15 ZENER
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
Characteristic
Output Voltage
V
in
= V
DD
or 0
“0” Level
Symbol
V
OL
V
DD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
“1” Level
V
IH
5.0
10
15
5.0
5.0
10
15
I
OL
5.0
10
15
15
−
5.0
10
15
5.0
10
15
− 55_C
Min
−
−
−
4.95
9.95
14.95
−
−
−
3.5
7.0
11
–1.2
–0.25
–0.62
–1.8
0.64
1.6
4.2
−
−
−
−
−
Max
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
−
−
−
−
−
−
−
−
−
−
±0.1
−
5.0
10
20
Min
−
−
−
4.95
9.95
14.95
−
−
−
3.5
7.0
11
–1.0
–0.2
–0.5
–1.5
0.51
1.3
3.4
−
−
−
−
−
25_C
Typ
0
0
0
5.0
10
15
2.25
4.50
6.75
2.75
5.50
8.25
–1.7
–0.36
–0.9
–3.5
0.88
2.25
8.8
±0.00001
5.0
0.005
0.010
0.015
Max
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
−
−
−
−
−
−
−
−
−
−
±0.1
7.5
5.0
10
20
−
−
−
4.95
9.95
14.95
−
−
−
3.5
7.0
11
–0.7
–0.14
–0.35
–1.1
0.36
0.9
2.4
−
−
−
−
−
125_C
Min
Max
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
−
−
−
−
−
−
−
−
−
−
±1.0
−
150
300
600
mAdc
Vdc
Unit
Vdc
“1” Level
V
in
= 0 or V
DD
Input Voltage (Note 2)
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
Output Drive Current
(V
OH
= 2.5 Vdc)
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OL
= 0.4 Vdc)
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
Input Current
Input Capacitance
Quiescent Current
(Per Package) Inh =
PCA
in
= V
DD
,
Zener = VCO
in
= 0 V, PCB
in
= V
DD
or 0 V, I
out
= 0
mA
Total Supply Current (Note 3)
(Inh = “0”, f
o
= 10 kHz, C
L
= 50 pF,
R1 = 1.0 MW, R2 =
R
R
SF
=
∞,
and 50% Duty Cycle)
“0” Level
V
OH
Vdc
V
IL
Vdc
I
OH
Source
mAdc
Sink
I
in
C
in
I
DD
mAdc
pF
mAdc
I
T
I
T
= (1.46
mA/kHz)
f + I
DD
I
T
= (2.91
mA/kHz)
f + I
DD
I
T
= (4.37
mA/kHz)
f + I
DD
mAdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Noise immunity specified for worst−case input combination.
Noise Margin for both “1” and “0” level =
1.0 Vdc min @ V
DD
= 5.0 Vdc
2.0 Vdc min @ V
DD
= 10 Vdc
2.5 Vdc min @ V
DD
= 15 Vdc
3. To Calculate Total Current in General:
VCO
in
– 1.65
3/4
VCO
in
– 1.65
V
DD
− 1.35
3/4
I
T
[
2.2 x V
DD
+
+ 1.6 x
+ 1 x 10
−3
(C
L
+ 9) V
DD
f +
R1
R2
R
SF
1 x 10
−1
V
DD2
100% Duty Cycle of PCA
in
100
+ I
Q
where: I
T
in
mA,
C
L
in pF, VCO
in
, V
DD
in Vdc, f in kHz, and
R1, R2, R
SF
in MW, C
L
on VCO
out
.
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2
MC14046B
ELECTRICAL CHARACTERISTICS
(Note 4) (C
L
= 50 pF, T
A
= 25°C)
Characteristic
Output Rise Time
t
TLH
= (3.0 ns/pF) C
L
+ 30 ns
t
TLH
= (1.5 ns/pF) C
L
+ 15 ns
t
TLH
= (1.1 ns/pF) C
L
+ 10 ns
Output Fall Time
t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
PHASE COMPARATORS 1 and 2
Input Resistance − PCA
in
R
in
5.0
10
15
15
5.0
10
15
5 to 15
1.0
0.2
0.1
150
−
−
−
2.0
0.4
0.2
1500
200
400
700
See Noise Immunity
−
−
−
−
300
600
1050
MW
Symbol
t
TLH
5.0
10
15
t
THL
5.0
10
15
−
−
−
100
50
37
175
75
55
−
−
−
180
90
65
350
150
110
ns
V
DD
Vdc
Minimum
Device
Typical
Maximum
Device
Units
ns
− PCB
in
Minimum Input Se−sitivity
AC Coupled — PCA
in
C series = 1000 pF, f = 50 kHz
DC Coupled − PCA
in
, PCB
in
VOLTAGE CONTROLLED OSCILLATOR (VCO)
Maximum Frequency
(VCO
in
= V
DD
, C1 = 50 pF
R1 = 5.0 kW, and R2 =
∞)
Temperature − Frequency Stability
(R2 =
∞ )
Linearity (R2 =
∞ )
(VCO
in
= 2.5 V
±
0.3 V, R1 > 10 kW)
(VCO
in
= 5.0 V
±
2.5 V, R1 > 400 kW)
(VCO
in
= 7.5 V
±
5.0 V, R1
≥
1000 kW)
Output Duty Cycle
Input Resistance − VCO
in
SOURCE−FOLLOWER
Offset Voltage
(VCO
in
minus SF
out
, RSF > 500 kW)
Linearity
(VCO
in
= 2.5 V
±
0.3 V, R
SF
> 50 kW)
(VCO
in
= 5.0 V
±
2.5 V, R
SF
> 50 kW)
(VCO
in
= 7.5 V
±
5.0 V, R
SF
> 50 kW)
ZENER DIODE
Zener Voltage (I
z
= 50
mA)
Dynamic Resistance (I
z
= 1.0 mA)
4. The formula given is for the typical characteristics only.
R
in
V
in
MW
mV p–p
−
f
max
5.0
10
15
5.0
10
15
5.0
10
15
0.5
1.0
1.4
−
−
−
−
−
−
−
150
0.7
1.4
1.9
0.12
0.04
0.015
1.0
1.0
1.0
50
1500
−
−
−
−
−
−
−
−
−
−
−
MHz
−
%/_C
−
%
−
R
in
5 to 15
15
%
MW
−
5.0
10
15
5.0
10
15
−
−
−
−
−
−
1.65
1.65
1.65
0.1
0.6
0.8
2.2
2.2
2.2
−
−
−
V
−
%
V
Z
R
Z
−
−
6.7
−
7.0
100
7.3
−
V
W
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3
MC14046B
PHASE COMPARATOR 1
Input Stage
00
X X
11
PCA
in
PCB
in
0
1
10
01
PC1
out
PHASE COMPARATOR 2
Input Stage
X X
01
00
PCB
in
10
11
10
00
01
11
01
00
10
11
PCA
in
PC2
out
LD (Lock Detect)
Refer to Waveforms in Figure 3.
0
0
3−State
Output Disconnected
1
1
0
Figure 1. Phase Comparators State Diagrams
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
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Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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Î
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Î
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Î
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Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Characteristic
Using Phase Comparator 1
Using Phase Comparator 2
No signal on input PCA
in
.
VCO in PLL system adjusts to center
frequency (f
0
).
VCO in PLL system adjusts to minimum
frequency (f
min
).
Phase angle between PCA
in
and PCB
in
.
90° at center frequency (f
0
), approaching
0_ and 180° at ends of lock range (2f
L
)
Yes
Always 0_ in lock (positive rising edges).
Locks on harmonics of center frequency.
Signal input noise rejection.
Lock frequency range (2f
L
).
No
High
Low
The frequency range of the input signal on which the loop will stay locked if it was
initially in lock; 2f
L
= full VCO frequency range = f
max
– f
min
.
Capture frequency range (2f
C
).
The frequency range of the input signal on which the loop will lock if it was initially
out of lock.
Depends on low−pass filter characteristics
(see Figure 3). f
C
v
f
L
f
C
= f
L
Center frequency (f
0
).
The frequency of VCO
out
, when VCO
in
= 1/2 V
DD
f
min
=
1
VCO output frequency (f).
R
2
(C
1
+ 32 pF)
1
(V
CO
input = V
SS
)
Note: These equations are intended to be
a design guide. Since calculated component
values may be in error by as much as a
factor of 4, laboratory experimentation may
be required for fixed designs. Part to part
frequency variation with identical passive
components is typically less than
±
20%.
f
max
=
R
1
(C
1
+ 32 pF)
+ f
min
(V
CO
input = V
DD
)
Where: 10K
v
R
1
v
1 M
10K
v
R
2
v
1 M
100pF
v
C
1
v
.01
mF
Figure 2. Design Information
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4
MC14046B
9
VCO
in
PCA
in
@ FREQUENCY f′
PCB
in
14
3
PHASE
2 OR 13
COMPARATOR PC1
out
OR
PC2
out
EXTERNAL
LOW-PASS
FILTER
9
11
R1
EXTERNAL
÷
N
COUNTER
R2
CI
SOURCE
FOLLOWER
10
R
SF
VCO
12
6
CI
A
4
7
CI
B
VCO
out
@ FREQUENCY Nf′ = f
SF
out
Typical Low−Pass Filters
(a)
INPUT
R3
OUTPUT
C2
2fC
[
1
p
2
p
fL
R3 C2
(a)
INPUT
R3
OUTPUT
R4
C2
Typically:
N
R4 C2
+
6N –
fmax 2
p D
f
(R3
)
3, 000W) C2
+
100NDf – R4 C2
fmax2
D
f = f
max
− f
min
NOTE: Sometimes R3 is split into two series resistors each R3
÷
2. A capacitor C
C
is then placed from the midpoint to ground. The value for
C
C
should be such that the corner frequency of this network does not significantly affect
W
n
. In Figure B, the ratio of R3 to R4 sets
the damping, R4
^
(0.1)(R3) for optimum results.
LOW−PASS FILTER
Filter A
Definitions: N = Total division ratio in feedback loop
Kφ = V
DD
/π for Phase Comparator 1
Kφ = V
DD
/4
π
for Phase Comparator 2
2
p D
fVCO
KVCO
+
VDD – 2 V
2
p
fr
(at phase detector input)
for a typical design
W
n
^
10
ζ
^
0.707
w
n
+
K
f
KVCO
NR3C2
w
n
+
Filter B
K
f
KVCO
NC2(R3
)
R4)
N
)
K
f
KVCO
z
+
Nwn
2K
f
KVCO
1
R3C2S
)
1
z
+
0.5
w
n (R3C2
)
F(s)
+
F(s)
+
R3C2S
)
1
S(R3C2
)
R4C2)
)
1
Waveforms
Phase Comparator 1
PCA
in
V
DD
V
SS
V
OH
PCB
in
PC1
out
VCO
in
V
OL
V
OH
V
OL
V
OH
V
OL
VCO
in
Note: for further information, see:
(1) F. Gardner, “Phase−Lock Techniques”, John Wiley and Son, New York, 1966.
(2) G. S. Moschytz, “Miniature RC Filters Using Phase−Locked Loop”, BSTJ, May, 1965.
(3) Garth Nash, “Phase−Lock Loop Design Fundamentals”, AN−535, Motorola Inc.
(4) A. B. Przedpelski, “Phase−Locked Loop Design Articles”, AR254, reprinted by Motorola Inc.
PCB
in
LD
PC2
out
PCA
in
Phase Comparator 2
V
DD
V
SS
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
Figure 3. General Phase−Locked Loop Connections and Waveforms
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