NXP Semiconductors
Data Sheet: Technical Data
Document Number: IMX6DQCPOPEC
Rev. 1, 09/2017
i.MX 6Dual/6Quad
Applications Processors
Consumer - PoP
MCIMX6Q5ExxxxD
MCIMX6Q7CxxxxD
MCIMX6Q5ExxxxE
MCIMX6Q7CxxxxE
MCIMX6D5ExxxxD
MCIMX6D7CxxxxD
MCIMX6D5ExxxxE
MCIMX6D7CxxxxE
Package Information
Plastic Package
12 x 12 mm, 0.4 mm pitch
Ordering Information
See
Table 1
1
Introduction
1
The i.MX 6Dual/6Quad processors are part of a growing
family of multimedia-focused products that offer high
performance processing and are optimized for lowest
power consumption.
The i.MX 6Dual/6Quad processors feature advanced
implementation of the quad ARM
®
Cortex
®
-A9 core,
which operates at speeds up to 800 MHz. They include
2D and 3D graphics processors, 1080p video processing,
and integrated power management. Each processor
provides a 2
×
32-bit LPDDR2-800 memory interface
and a number of other interfaces for connecting
peripherals, such as WLAN, Bluetooth
®
, GPS, hard
drive, displays, and camera sensors.
The i.MX 6Dual/6Quad processors are specifically
useful for applications such as the following:
• High-end mobile Internet devices (MID)
• High-end PDAs
• High-end portable media players (PMP) with HD
video capability
2
3
4
5
6
7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Signal Naming Convention . . . . . . . . . . . . . . . . . . . 7
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Special Signal Considerations. . . . . . . . . . . . . . . . 18
3.2 Recommended Connections for Unused Analog
Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . . 19
4.2 Power Supplies Requirements and Restrictions . . 32
4.3 Integrated LDO Voltage Regulator Parameters . . . 33
4.4 PLL Electrical Characteristics . . . . . . . . . . . . . . . . 35
4.5 On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . . 36
4.6 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 37
4.7 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 41
4.8 Output Buffer Impedance Parameters . . . . . . . . . . 45
4.9 System Modules Timing . . . . . . . . . . . . . . . . . . . . 48
4.10 Multi-Mode DDR Controller (MMDC). . . . . . . . . . . 60
4.11 General-Purpose Media Interface (GPMI) Timing. 60
4.12 External Peripheral Interface Parameters . . . . . . . 69
Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . 130
5.1 Boot Mode Configuration Pins. . . . . . . . . . . . . . . 130
5.2 Boot Devices Interfaces Allocation . . . . . . . . . . . 131
Package Information and Contact Assignments . . . . . . 133
6.1 Signal Naming Convention . . . . . . . . . . . . . . . . . 133
6.2 12 x 12 mm Package on Package (PoP)
Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
NXP Reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products
Introduction
•
•
Gaming consoles
Portable navigation devices (PND)
The i.MX 6Dual/6Quad processors offers numerous advanced features, such as:
• Applications processors—The processors enhance the capabilities of high-tier portable
applications by fulfilling the ever increasing MIPS needs of operating systems and games. The
Dynamic Voltage and Frequency Scaling (DVFS) provides significant power reduction, allowing
the device to run at lower voltage and frequency with sufficient MIPS for tasks such as audio
decode.
• Multilevel memory system—The multilevel memory system of each processor is based on the L1
instruction and data caches, L2 cache, and internal and external memory. The processors support
many types of external memory devices, including LPDDR2, NOR Flash, PSRAM, cellular RAM,
NAND Flash (MLC and SLC), OneNAND™, and managed NAND, including eMMC up to rev
4.4/4.41.
• Smart speed technology—The processors have power management throughout the device that
enables the rich suite of multimedia features and peripherals to consume minimum power in both
active and various low power modes. Smart speed technology enables the designer to deliver a
feature-rich product, requiring levels of power far lower than industry expectations.
• Dynamic voltage and frequency scaling—The processors improve the power efficiency of devices
by scaling the voltage and frequency to optimize performance.
• Multimedia powerhouse—The multimedia performance of each processor is enhanced by a
multilevel cache system, Neon
®
MPE (Media Processor Engine) co-processor, a multi-standard
hardware video codec, 2 autonomous and independent image processing units (IPU), and a
programmable smart DMA (SDMA) controller.
• Powerful graphics acceleration—Each processor provides three independent, integrated graphics
processing units: an OpenGL
®
ES .0 3D graphics accelerator with four shaders (up to MTri/s and
OpenCL support), 2D graphics accelerator, and dedicated OpenVG™ 1.1 accelerator.
• Interface flexibility—Each processor supports connections to a variety of interfaces: LCD
controller for up to four displays (including parallel display, HDMI1.4, MIPI display, and LVDS
display), dual CMOS sensor interface (parallel or through MIPI), high-speed USB on-the-go with
PHY, high-speed USB host with PHY, multiple expansion card ports (high-speed MMC/SDIO host
and other), 10/100/1000 Mbps Gigabit Ethernet controller, and a variety of other popular interfaces
(such as UART, I
2
C, and I
2
S serial audio, SATA-II, and PCIe-II).
• Advanced security—The processors deliver hardware-enabled security features that enable secure
e-commerce, digital rights management (DRM), information encryption, secure boot, and secure
software downloads. The security features are discussed in detail in the i.MX 6Dual/6Quad
security reference manual (IMX6DQ6SDLSRM).
• Integrated power management—The processors integrate linear regulators and internally generate
voltage levels for different domains. This significantly simplifies system power management
structure.
i.MX 6Dual/6Quad Applications Processors Consumer - PoP, Rev. 1, 09/2017
2
NXP Semiconductors
Introduction
1.1
Ordering Information
Table 1
shows examples of orderable part numbers covered by this data sheet. This table does not include
all possible orderable part numbers. The latest part numbers are available on
nxp.com/imx6series.
If your
desired part number is not listed in the table, or you have questions about available parts, see
nxp.com/imx6series
or contact your NXP representative.
Table 1. Orderable Part Numbers
Part Number
MCIMX6Q5EZK08AD
Quad/Dual
CPU
i.MX 6Quad
Options
MLB not
supported
MLB not
supported
MLB not
supported
MLB not
supported
MLB not
supported
MLB not
supported
MLB not
supported
MLB not
supported
Speed
Grade
800
MHz
800
MHz
800
MHz
800
MHz
800
MHz
800
MHz
800
MHz
800
MHz
Temperature
Grade
Extended
Commercial
Extended
Commercial
Industrial
Package
12 mm x 12 mm, 0.4 mm pitch,
FCPBGA,
Package on Package (PoP)
12 mm x 12 mm, 0.4 mm pitch,
FCPBGA,
Package on Package (PoP)
12 mm x 12 mm, 0.4 mm pitch,
FCPBGA,
Package on Package (PoP)
12 mm x 12 mm, 0.4 mm pitch,
FCPBGA,
Package on Package (PoP)
12 mm x 12 mm, 0.4 mm pitch,
FCPBGA,
Package on Package (PoP)
12 mm x 12 mm, 0.4 mm pitch,
FCPBGA,
Package on Package (PoP)
12 mm x 12 mm, 0.4 mm pitch,
FCPBGA,
Package on Package (PoP)
12 mm x 12 mm, 0.4 mm pitch,
FCPBGA,
Package on Package (PoP)
MCIMX6Q5EZK08AE
i.MX 6Quad
MCIMX6Q7CZK08AD
i.MX 6Quad
MCIMX6Q7CZK08AE
i.MX 6Quad
Industrial
MCIMX6D5EZK08AD
i.MX 6Dual
Extended
Commercial
Extended
Commercial
Industrial
MCIMX6D5EZK08AE
i.MX 6Dual
MCIMX6D7CZK08AD
i.MX 6Dual
MCIMX6D7CZK08AE
i.MX 6Dual
Industrial
Figure 1
describes the part number nomenclature to identify the characteristics of the specific part number
you have (for example, cores, frequency, temperature grade, fuse options, silicon revision).
Figure 1
applies to the i.MX 6Dual/6Quad.
The two characteristics that identify which data sheet a specific part applies to are the part number series
field and the temperature grade (junction) field:
• The i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors data sheet
(IMX6DQAEC) covers parts listed with “A (Automotive temp)”
• The i.MX 6Dual/6Quad Applications Processors for Consumer Products data sheet (IMX6DQCEC)
covers parts listed with “D (Commercial temp)” or “E (Extended Commercial temp)”
i.MX 6Dual/6Quad Applications Processors Consumer - PoP, Rev. 1, 09/2017
NXP Semiconductors
3
Introduction
•
•
The i.MX 6Dual/6Quad Applications Processors for Consumer Products data sheet
(IMX6DQCPOPEC) covers parts listed with “D (Commercial temp)” or “E (Extended Commercial
temp)” and that uses the Package-on-Package.
The i.MX 6Dual/6Quad Applications Processors for Industrial Products data sheet (IMX6DQIEC)
covers parts listed with “C (Industrial temp)”
Ensure that you have the right data sheet for your specific part by checking the temperature grade
(junction) field and matching it to the right data sheet. If you have questions, see nxp.com/imx6series or
contact your NXP representative.
MC
Qualification level
Prototype Samples
Mass Production
Special
IMX6
MC
PC
MC
SC
X
@
+
VV
$$
%
A
Silicon revision
1
Rev 1.2
Rev 1.3
Rev 1.6
A
C
D
E
Part # series
i.MX 6Quad
i.MX 6Dual
X
Q
D
Fusing
Default Setting
HDCP Enabled
%
A
C
Frequency
Part differentiator
Package
Industrial
Extended
Commercial
ZK
ZK
VPU
Y
Y
GPU
Y
Y
MLB
N
N
7
5
$$
08
@
800 MHz
2
Package type
FCPBGA PoP 12x12 0.4mm
RoHS
ZK
Temperature Tj
Extended commercial: -20 to + 105
°
C
Industrial: -40 to +105
°
C
1. See the nxp.com\imx6series Web page for latest information on the available silicon revision.
2. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 792 MHz.
+
E
C
Figure 1. Part Number Nomenclature—i.MX 6Dual PoP and 6Quad PoP
1.2
Features
The i.MX 6Dual/6Quad processors are based on ARM Cortex-A9 MPCore platform, which has the
following features:
• ARM Cortex-A9 MPCore 4xCPU processor (with TrustZone
®
)
• The core configuration is symmetric, where each core includes:
i.MX 6Dual/6Quad Applications Processors Consumer - PoP, Rev. 1, 09/2017
4
NXP Semiconductors
Introduction
—
—
—
—
32 KByte L1 Instruction Cache
32 KByte L1 Data Cache
Private Timer and Watchdog
Cortex-A9 NEON MPE (Media Processing Engine) Co-processor
The ARM Cortex-A9 MPCore complex includes:
• General Interrupt Controller (GIC) with 128 interrupt support
• Global Timer
• Snoop Control Unit (SCU)
• 1 MB unified I/D L2 cache, shared by two/four cores
• Two Master AXI (64-bit) bus interfaces output of L2 cache
• Frequency of the core (including Neon and L1 cache) as per
Table 6.
• NEON MPE coprocessor
— SIMD Media Processing Architecture
— NEON register file with 32x64-bit general-purpose registers
— NEON Integer execute pipeline (ALU, Shift, MAC)
— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
— NEON load/store and permute pipeline
The SoC-level memory system consists of the following additional components:
• Boot ROM, including HAB (96 KB)
• Internal multimedia / shared, fast access RAM (OCRAM, 256 KB)
• Secure/non-secure RAM (16 KB)
• External memory interfaces:
— 2
×
32-bit, LPDDR2-800 channels supporting DDR interleaving mode
— 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size,
BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 40 bit.
— 16/32-bit NOR Flash. All EIMv2 pins are muxed on other interfaces.
— 16/32-bit PSRAM, Cellular RAM
Each i.MX 6Dual/6Quad processor enables the following interfaces to external devices (some of them are
muxed and not available simultaneously):
• Hard Disk Drives—SATA II, 3.0 Gbps
• Displays—Total five interfaces available. Total raw pixel rate of all interfaces is up to 450
Mpixels/sec, 24 bpp. Up to four interfaces may be active in parallel.
— One Parallel 24-bit display port, up to 225 Mpixels/sec (for example, WUXGA at 60 Hz or dual
HD1080 and WXGA at 60 Hz)
— LVDS serial ports—One port up to 170 Mpixels/sec (for example, WUXGA at 60 Hz) or two
ports up to 85 MP/sec each
— HDMI 1.4 port
— MIPI/DSI, two lanes at 1 Gbps
i.MX 6Dual/6Quad Applications Processors Consumer - PoP, Rev. 1, 09/2017
NXP Semiconductors
5
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