XR16M564/564D
1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO
MAY 2008
REV. 1.0.0
GENERAL DESCRIPTION
The XR16M564
1
(M564) is an enhanced quad
Universal Asynchronous Receiver and Transmitter
(UART) with 32 bytes of transmit and receive FIFOs,
programmable transmit and receive FIFO trigger
levels, automatic hardware and software flow control,
and data rates of up to 16 Mbps at 4X sampling rate.
Each UART has a set of registers that provide the
user with operating status and control, receiver error
indications, and modem serial interface controls. An
internal loopback capability allows onboard
diagnostics. The M564 is available in a 48-pin QFN,
64-pin LQFP, 68-pin PLCC and 80-pin LQFP
packages. The 64-pin and 80-pin packages only offer
the 16 mode interface, but the 48 and 68 pin
packages offer an additional 68 mode interface which
allows easy integration with Motorola processors.
The XR16M564IV (64-pin) offers three state interrupt
output while the XR16M564DIV provides continuous
interrupt output. The XR16M564 is compatible with
the industry standard ST16C554 and ST16C654/
654D.
N
OTE
:
1 Covered by U.S. Patent #5,649,122.
FEATURES
•
Pin-to-pin compatible with ST16C454, ST16C554,
TI’s TL16C754B and NXP’s SC16C754B
•
Intel or Motorola Data Bus Interface select
•
Four independent UART channels
■
■
■
■
■
■
■
■
■
■
Register Set Compatible to 16C550
Data rates of up to 16 Mbps
32 byte Transmit FIFO
32 byte Receive FIFO with error tags
4 Selectable TX and RX FIFO Trigger Levels
Automatic Hardware (RTS/CTS) Flow Control
Automatic Software (Xon/Xoff) Flow Control
Programmable Xon/Xoff characters
Wireless Infrared (IrDA 1.0) Encoder/Decoder
Full modem interface
•
1.62V to 3.63V supply operation
•
Sleep Mode with automatic wake-up
•
Crystal oscillator or external clock input
APPLICATIONS
•
Portable Appliances
•
Telecommunication Network Routers
•
Ethernet Network Routers
•
Cellular Data Devices
•
Factory Automation and Process Controls
F
IGURE
1. XR16M564 B
LOCK
D
IAGRAM
1.62V to 3.6V VCC
GND
UART Channel A
UART 32 Byte TX FIFO
Regs
IR
TX & RX
ENDEC
BRG
32 Byte RX FIFO
UART Channel B
(same as Channel A)
UART Channel C
(same as Channel A)
UART Channel D
(same as Channel A)
Crystal Osc/Buffer
A2:A0
D7:D0
IOR#
IOW#
CSA#
CSB#
CSC#
CSD#
INTA
INTB
INTC
INTD
TXRDY# A-D
RXRDY # A-D
Reset
16/68#
INTSEL
CLKSEL
TXA, RXA, DTRA#,
DSRA #, RTSA#, CTSA#,
CDA#, RIA#
Data Bus
Interface
TXB, RXB, DTRB#,
DSRB #, RTSB#, CTSB#,
CDB#, RIB#
TXC, RXC, DTRC#,
DSRC#, RTSC#, CTSC#,
CDC#, RIC#
TXD, RXD, DTRD#,
DSRD#, RTSD#, CTSD#,
CDD#, RID#
XTAL1
XTAL2
564 BLK
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XR16M564/564D
1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO
REV. 1.0.0
F
IGURE
2. P
IN
O
UT
A
SSIGNMENT
F
OR
68-
PIN
PLCC P
ACKAGES
I
N
16
AND
68 M
ODE AND
64-
PIN
LQFP P
ACKAGES
INTSEL
CDA#
RIA#
CDD#
CDA#
RID#
GND
VCC
RXD
RXA
D7
D6
D5
D4
D3
D2
D1
D0
68
67
66
65
64
63
62
RID#
GND
RIA#
RXA
68
67
66
65
64
63
62
63
9
8
7
6
5
4
3
2
1
DSRA#
CTSA#
DTRA#
VCC
RTSA#
INTA
CSA#
TXA
IOW#
TXB
CSB#
INTB
RTSB#
GND
DTRB#
CTSB#
DSRB#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
60
59
58
57
56
55
DSRD#
CTSD#
DTRD#
GND
RTSD#
INTD
CSD#
TXD
IOR#
TXC
CSC#
INTC
RTSC#
VCC
DTRC#
CTSC#
DSRC#
DSRA#
CTSA#
DTRA#
VCC
RTSA#
IRQ#
CS#
TXA
R/W#
TXB
A3
N.C.
RTSB#
GND
DTRB#
CTSB#
DSRB#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
63
9
8
7
6
5
4
3
2
1
CDD#
GND
VCC
RXD
D7
D6
D5
D4
D3
D2
D1
D0
60
59
58
57
56
55
DSRD#
CTSD#
DTRD#
GND
RTSD#
N.C.
N.C.
TXD
N.C.
TXC
A4
N.C.
RTSC#
VCC
DTRC#
CTSC#
DSRC#
XR16M564
68-pin PLCC
Intel Mode
(16/68# pin connected to VCC)
54
53
52
51
50
49
48
47
46
45
44
XR16M564
68-pin PLCC
Motorola Mode
(16/68# pin connected to GND)
54
53
52
51
50
49
48
47
46
45
44
16/68#
TXRDY#
CDB#
CLKSEL
RXRDY#
RESET
XTAL1
XTAL2
TXRDY#
16/68#
CLKSEL
RXRDY#
RESET
XTAL1
XTAL2
CDC#
60
56
54
52
64
62
61
59
57
55
51
58
53
50
DSRA#
CTSA#
DTRA#
VCC
RTSA#
INTA
CSA#
TXA
IOW#
TXB
CSB#
INTB
RTSB#
GND
DTRB#
CTSB#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
21
29
23
22
25
26
27
28
30
31
17
20
18
19
24
32
63
49
CDD#
CDA#
GND
RXD
RID#
RXA
RIA#
D6
D5
D4
D3
D1
D0
VCC
D7
D2
48
47
46
45
44
43
DSRD#
CTSD#
DTRD#
GND
RTSD#
INTD
CSD#
TXD
IOR#
TXC
CSC#
INTC
RTSC#
VCC
DTRC#
CTSC#
XR16M564
64-pin TQFP
Intel Mode Only
42
41
40
39
38
37
36
35
34
33
CLKSEL
RIB#
DSRB#
CDB#
CDC#
RIC#
A1
A0
RESET
2
DSRC#
A2
XTAL1
XTAL2
RXB
GND
RXC
CDC#
CDB#
RIC#
RIB#
RIC#
RIB#
GND
RXB
GND
RXC
RXC
A2
A1
RXB
A2
A1
A0
A0
XR16M564/564D
REV. 1.0.0
1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO
F
IGURE
3. P
IN
O
UT
A
SSIGNMENT
F
OR
48-
PIN
QFN P
ACKAGE AND
80-
PIN
LQFP P
ACKAGE
47 GND
38 INTSEL
46 D7
45 D6
44 D5
48
42
39 D0
37 VCC
RXA
43 D4
41 D2
40 D1
D3
CTSA#
VCC
RTSA#
INTA
CSA#
TXA
IOW#
TXB
CSB#
INTB
RTSB#
CTSB#
1
2
3
4
5
6
7
8
9
10
11
12
15
18
19
20
21
22
13
14
16
17
23
24
36
35
34
33
RXD
CTSD#
GND
RTSD#
INTD
XR16M564
48-pin QFN
32
31 CSD#
30
29
28
27
26
25
TXD
IOR#
TXC
CSC#
INTC
RTSC#
RESET
XTAL1
16/68#
RXB
XTAL2
GND
A1
DSRD#
DTRD#
CTSD#
CTSC#
VCC
RXC
A2
A0
RTSD#
CTSC#
RTSC#
INTD
GND
DTRC#
NC
NC
DSRC#
62
CSD#
IOR#
CSC#
INTC
VCC
TXD
TXC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
NC
C DD#
RID#
1
2
3
61
NC
60
59
58
57
56
NC
C DC#
RIC#
RXC
GND
TXR DY#
RX RDY#
RESET
NC
XTAL2
XTAL1
NC
A0
A1
A2
VC C
RXB
RIB#
CDB#
NC
RXD
VCC
INTS EL
D0
D1
D2
NC
D3
D4
D5
D6
D7
G ND
RXA
RIA#
CDA #
NC
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
55
54
53
XR 16M 564
80 - pin LQFP
Intel Mode Only
52
51
50
49
48
47
46
45
44
43
42
41
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
DSRB#
DTRA #
CTSA#
RTSB#
RTSA#
CSA#
IOW#
CSB#
DTRB#
CTSB#
TXB
INTB
TXA
NC
DSRA
INTA
3
GND
VCC
NC
NC
40
#
XR16M564/564D
1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO
ORDERING INFORMATION
P
ART
N
UMBER
XR16M564IJ68
XR16M564IV64
XR16M564DIV64
XR16M564IL48
XR16M564IV80
P
ACKAGE
68-Lead PLCC
64-Lead LQFP
64-Lead LQFP
48-pin QFN
80-Lead LQFP
O
PERATING
T
EMPERATURE
R
ANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
D
EVICE
S
TATUS
Active
Active
Active
Active
Active
REV. 1.0.0
PIN DESCRIPTIONS
Pin Description
N
AME
48-QFN
P
IN
#
64-LQFP 68-PLCC 80-LQFP
T
YPE
P
IN
#
P
IN
#
P
IN
#
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
(VCC)
15
16
17
46
45
44
43
42
41
40
39
29
22
23
24
60
59
58
57
56
55
54
53
40
32
33
34
5
4
3
2
1
68
67
66
52
46
47
48
15
14
13
12
11
9
8
7
70
I
Address data lines [2:0]. These 3 address lines select
one of the internal registers in UART channel A-D dur-
ing a data bus transaction.
Data bus lines [7:0] (bidirectional).
I/O
I
When 16/68# pin is HIGH, the Intel bus interface is
selected and this input becomes read strobe (active
low). The falling edge instigates an internal read cycle
and retrieves the data byte from an internal register
pointed by the address lines [A2:A0], puts the data
byte on the data bus to allow the host processor to
read it on the rising edge.
When 16/68# pin is LOW, the Motorola bus interface is
selected and this input is not used and should be con-
nected to VCC.
When 16/68# pin is HIGH, it selects Intel bus interface
and this input becomes write strobe (active low). The
falling edge instigates the internal write cycle and the
rising edge transfers the data byte on the data bus to
an internal register pointed by the address lines.
When 16/68# pin is LOW, the Motorola bus interface is
selected and this input becomes read (logic 1) and
write (LOW) signal.
When 16/68# pin is HIGH, this input is chip select A
(active low) to enable channel A in the device.
When 16/68# pin is LOW, this input becomes the chip
select (active low) for the Motorola bus interface.
IOW#
(R/W#)
7
9
18
31
I
CSA#
(CS#)
5
7
16
28
I
4
XR16M564/564D
REV. 1.0.0
1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO
Pin Description
N
AME
CSB#
(A3)
48-QFN
P
IN
#
9
64-LQFP 68-PLCC 80-LQFP
T
YPE
P
IN
#
P
IN
#
P
IN
#
11
20
33
I
D
ESCRIPTION
When 16/68# pin is HIGH, this input is chip select B
(active low) to enable channel B in the device.
When 16/68# pin is LOW, this input becomes address
line A3 which is used for channel selection in the
Motorola bus interface.
When 16/68# pin is HIGH, this input is chip select C
(active low) to enable channel C in the device.
When 16/68# pin is LOW, this input becomes address
line A4 which is used for channel selection in the
Motorola bus interface.
When 16/68# pin is HIGH, this input is chip select D
(active low) to enable channel D in the device.
When 16/68# pin is LOW, this input is not used and
should be connected VCC.
CSC#
(A4)
27
38
50
68
I
CSD#
(VCC)
31
42
54
73
I
INTA
(IRQ#)
4
6
15
27
O
When 16/68# pin is HIGH for Intel bus interface, this
(OD) ouput becomes channel A interrupt output. The output
state is defined by the user and through the software
setting of MCR[3]. INTA is set to the active mode when
MCR[3] is set to a logic 1. INTA is set to the three state
mode when MCR[3] is set to a logic 0 (default). See
MCR[3].
When 16/68# pin is LOW for Motorola bus interface,
this output becomes device interrupt output (active
low, open drain). An external pull-up resistor is
required for proper operation.
O
When 16/68# pin is HIGH for Intel bus interface, these
ouputs become the interrupt outputs for channels B, C,
and D. The output state is defined by the user through
the software setting of MCR[3]. The interrupt outputs
are set to the active mode when MCR[3] is set to a
logic 1 and are set to the three state mode when
MCR[3] is set to a logic 0 (default). See MCR[3].
When 16/68# pin is LOW for Motorola bus interface,
these outputs are unused and will stay at logic zero
level. Leave these outputs unconnected.
Transmitter Ready (active low). This output is a logi-
cally ANDed status of TXRDY# A-D. See
Table 5.
If
this output is unused, leave it unconnected.
Receiver Ready (active low). This output is a logically
ANDed status of RXRDY# A-D. See
Table 5.
If this
output is unused, leave it unconnected.
INTB
INTC
INTD
(N.C.)
10
26
32
12
37
43
21
49
55
34
67
74
TXRDY#
-
-
39
55
O
RXRDY#
-
-
38
54
O
5
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