or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1-1
DS1040
Introduction_01.1
Introduction
iCE40 LP/HX Family Data Sheet
Table 1-1. iCE40 Family Selection Guide (Cont.)
LP384
Package
100 VQFP
(14 x 14mm, 0.5mm)
121 ucBGA
(5 x 5mm, 0.4mm)
121 csBGA
(6 x 6mm, 0.5mm)
132 csBGA
(8 x 8mm, 0.5mm)
144 TQFP
(20 x 20mm, 0.5mm)
225 ucBGA
(7 x 7mm, 0.4mm)
256-ball caBGA
(14 x 14mm, 0.8mm)
Code
VQ100
CM121
CB121
CB132
TQ144
CM225
CT256
167 (20)
178 (23)
95 (12)
92 (12)
95(11)
96(12)
95(12)
107(14)
178(23)
206(26)
95(12)
93 (13)
93 (13)
LP1K
LP4K
LP8K
HX1K
HX4K
HX8K
Programmable I/O: Max Inputs (LVDS25)
72(9)
1
1. No PLL available on the 36 ucBGA, 81 csBGA, 84 QFN and 100 VQFP packages.
2. Only one PLL available on the 81 ucBGA package.
Introduction
The iCE40 family of ultra-low power, non-volatile FPGAs has four devices with densities ranging from 384 to 7680
Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic, these devices feature Embedded
Block RAM (EBR), Non-volatile Configuration Memory (NVCM) and Phase Locked Loops (PLLs). These features
allow the devices to be used in low-cost, high-volume consumer and system applications.
The iCE40 devices are fabricated on a 40 nm CMOS low power process. The device architecture has several fea-
tures such as programmable low-swing differential I/Os and the ability to turn off on-chip PLLs dynamically. These
features help manage static and dynamic power consumption, resulting in low static power for all members of the
family. The iCE40 devices are available in two versions – ultra low power (LP) and high performance (HX) devices.
The iCE40 FPGAs are available in a broad range of advanced halogen-free packages ranging from the space sav-
ing 2.5x2.5 mm micro chip-scale BGA to the PCB-friendly 20x20 mm TQFP. Table 1-1 shows the LUT densities,
package and I/O options, along with other key parameters.
The iCE40 devices offer enhanced I/O features such as pull-up resistors. Pull-up features are controllable on a
“per-pin” basis.
The iCE40 devices also provide flexible, reliable and secure configuration from on-chip NVCM. These devices can
also configure themselves from external SPI Flash or be configured by an external master such as a CPU.
Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the iCE40
family of devices. Popular logic synthesis tools provide synthesis library support for iCE40. Lattice design tools use
the synthesis tool output along with the user-specified preferences and constraints to place and route the design in
the iCE40 device. These tools extract the timing from the routing and back-annotate it into the design for timing ver-
ification.
Lattice provides many pre-engineered IP (Intellectual Property) modules, including a number of reference designs,
licensed free of charge, optimized for the iCE40 FPGA family. By using these configurable soft core IP cores as
standardized blocks, users are free to concentrate on the unique aspects of their design, increasing their productiv-
ity.
1-2
iCE40 LP/HX Family Data Sheet
Architecture
April 2013
Data Sheet DS1040
Architecture Overview
The iCE40 family architecture contains an array of Programmable Logic Blocks (PLB), sysCLOCK™ PLLs, Non-
volatile Programmable Configuration Memory (NVCM) and blocks of sysMEM™ Embedded Block RAM (EBR) sur-
rounded by Programmable I/O (PIO). Figure 2-1 shows the block diagram of the iCE40-1K device.
Figure 2-1. iCE40-1K Device, Top View
Programmable
Logic Block (PLB)
I/O Bank 0
Programmable Interconnect
PLB
PLB
PLB
PLB
PLB
PLB
PLB
Programmable Interconnect
4Kbit RAM
PLB
Programmable Interconnect
NVCM
PLL
I/O Bank 2
SPI
Bank
Carry Logic
4-Input Look-up
Table (LUT4)
Non-volatile
Configuration Memory
(NVCM)
Phase-Locked
Loop
Flip-flop
with
Enable
and Reset Controls
The logic blocks, Programmable Logic Blocks (PLB) and sysMEM EBR blocks, are arranged in a two-dimensional
grid with rows and columns. Each column has either logic blocks or EBR blocks. The PIO cells are located at the
periphery of the device, arranged in banks. The PLB contains the building blocks for logic, arithmetic, and register
functions. The PIOs utilize a flexible I/O buffer referred to as a sysIO buffer that supports operation with a variety of
interface standards. The blocks are connected with many vertical and horizontal routing channel resources. The
place and route software tool automatically allocates these routing resources.
In the iCE40 family, there are up to four independent sysIO banks. Note on some packages V
CCIO
banks are tied
together. There are different types of I/O buffers on the different banks. Refer to the details in later sections of this
document. The sysMEM EBRs are large 4 Kbit, dedicated fast memory blocks. These blocks can be configured as
RAM, ROM or FIFO.
The iCE40 architecture also provides up to two sysCLOCK Phase Locked Loop (PLL) blocks. The PLLs have mul-
tiply, divide, and phase shifting capabilities that are used to manage the frequency and phase relationships of the
clocks.
Every device in the family has a SPI port that supports programming and configuration of the device. The iCE40
includes on-chip, Nonvolatile Configuration Memory (NVCM).
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
2-1
8
Logic Cells = Programmable Logic Block
PLB
PLB
PLB
PLB
PLB
PLB
PLB
I/O Bank 3
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
4Kbit RAM
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
I/O Bank 1
DS1040
Architecture_01.1
Architecture
iCE40 LP/HX Family Data Sheet
PLB Blocks
The core of the iCE40 device consists of Programmable Logic Blocks (PLB) which can be programmed to perform
logic and arithmetic functions. Each PLB consists of eight interconnected Logic Cells (LC) as shown in Figure 2-2.
Each LC contains one LUT and one register.
Figure 2-2. PLB Block Diagram
Shared Block-Level Controls
Programmable Logic
Block (PLB)
FCOUT
Set/Reset
0
Clock
Enable
1
Logic Cell
Carry Logic
DFF
I0
D
EN
Q
SR
O
8
Logic Cells (LCs)
I1
I2
I3
LUT4
FCIN
Four-input
Look-Up Table
(LUT4)
Flip-flop
with
optional enable and
set or reset controls
= Statically defined
by
configuration program
Logic Cells
Each Logic Cell includes three primary logic elements shown in Figure 2-2.
• A four-input Look-Up Table (LUT4) builds any combinational logic function, of any complexity, requiring up to
four inputs. Similarly, the LUT4 element behaves as a 16x1 Read-Only Memory (ROM). Combine and cas-
cade multiple LUT4s to create wider logic functions.
• A ‘D’-style Flip-Flop (DFF), with an optional clock-enable and reset control input, builds sequential logic func-
tions. Each DFF also connects to a global reset signal that is automatically asserted immediately following
device configuration.
• Carry Logic boosts the logic efficiency and performance of arithmetic functions, including adders, subtracters,
comparators, binary counters and some wide, cascaded logic functions.
Table 2-1. Logic Cell Signal Descriptions
Function
Input
Input
Input
Input
Input
Output
Output
Type
Data signal
Control signal
Control signal
Control signal
Inter-PLB signal
Data signals
Inter-PFU signal
Signal Names
I0, I1, I2, I3
Enable
Set/Reset
1
Clock
FCIN
O
FCOUT
Inputs to LUT4
Clock enable shared by all LCs in the PLB
Asynchronous or synchronous local set/reset shared by all LCs in
the PLB.
Clock one of the eight Global Buffers, or from the general-purpose
interconnects fabric shared by all LCs in the PLB
Fast carry in
LUT4 or registered output
Fast carry out
Description
1. If Set/Reset is not used, then the flip-flop is never set/reset, except when cleared immediately after configuration.
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