Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
ÎÎÎ
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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Î
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Î
Î
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MAXIMUM RATINGS
Symbol
V
CC
V
out
T
stg
V
IN
I
CC
I
OK
I
out
P
D
I
IK
Storage Temperature
Power Dissipation
DC Supply Current, V
CC
and GND Pins
DC Output Current, per Pin
Output Diode Current
Input Diode Current
DC Output Voltage
DC Input Voltage
DC Supply Voltage
Parameter
DC ELECTRICAL CHARACTERISTICS
RECOMMENDED OPERATING CONDITIONS
Symbol
Symbol
Dt/DV
V
OH
V
CC
V
OL
V
out
V
IH
V
IN
I
CC
V
IL
T
A
I
in
Quiescent Supply Current
Input Leakage Current
Low−Level Output Voltage
(V
IN
= V
IH
or V
IL
)
High−Level Output Voltage
(V
IN
= V
IH
or V
IL
)
Low−Level Input Voltage
High−Level Input Voltage
Input Rise and Fall Time
Operating Temperature, All Package Types
DC Output Voltage
DC Input Voltage
DC Supply Voltage
Parameter
I
OL
= 50
mA
I
OL
= 50
mA
I
OL
= 4 mA
I
OH
= −50
mA
I
OH
= −50
mA
I
OH
= −4 mA
V
IN
= V
CC
or GND
V
IN
= 5.5 V or GND
Test Conditions
Parameter
http://onsemi.com
MC74LVX00
2
V
CC
V
3.6
3.6
2.0
3.0
3.0
2.0
3.0
3.0
2.0
3.0
3.6
2.0
3.0
3.6
1.9
2.9
2.58
Min
1.5
2.0
2.4
T
A
= 25°C
Typ
0.0
0.0
2.0
3.0
0.1
0.1
0.36
±0.1
0.5
0.8
0.8
Max
2.0
Min
−40
–0.5 to V
CC
+0.5
2.0
0
0
0
–65 to +150
–0.5 to +7.0
–0.5 to +7.0
T
A
= −40 to 85°C
1.9
2.9
2.48
Min
1.5
2.0
2.4
Value
180
−20
±50
±25
±20
Max
V
CC
+85
100
5.5
3.6
0.1
0.1
0.44
20.0
±1.0
0.5
0.8
0.8
Max
ns/V
Unit
Unit
Unit
mW
mA
mA
mA
mA
_C
_C
mA
mA
V
V
V
V
V
V
V
V
V
V
MC74LVX00
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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Î Î
Î
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Î
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î
Î
Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
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Î
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS
(Input t
r
= t
f
= 3.0 ns)
Symbol
t
PLH
,
t
PHL
Parameter
Test Conditions
T
A
= 25°C
Typ
5.4
7.9
4.1
6.6
T
A
= −40 to 85°C
Min
1.0
1.0
1.0
1.0
Max
Min
Max
Unit
ns
Propagation Delay, Input to
Output
V
CC
= 2.7 V
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 50 pF
C
L
= 50 pF
10.1
13.6
6.2
9.7
1.5
1.5
12.5
16.0
7.5
11.0
1.5
1.5
V
CC
= 3.3
±0.3
V
V
CC
= 2.7 V
V
CC
= 3.3
±0.3
V
t
OSHL
t
OSLH
Output−to−Output Skew
(Note 1)
ns
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t
OSHL
) or LOW−to−HIGH (t
OSLH
); parameter
guaranteed by design.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î
Î Î
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Î Î
Î
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ÎÎÎÎÎÎÎÎÎÎÎ Î
Î Î
Î Î
Î
Î Î Î
Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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Î ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î
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Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Î
Î
T
A
= 25°C
Typ
4
T
A
= −40 to 85°C
Min
Max
10
Symbol
Cin
Parameter
Min
Max
10
Unit
pF
pF
Input Capacitance
C
PD
Power Dissipation Capacitance (Note 2)
19
2. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
/ 4 (per gate). C
PD
is used to determine the
no−load dynamic power consumption; P
D
= C
PD
V
CC2
f
in
+ I
CC
V
CC
.
CAPACITIVE CHARACTERISTICS
NOISE CHARACTERISTICS
(Input t
r
= t
f
= 3.0 ns, C
L
= 50 pF, V
CC
= 3.3 V, Measured in SOIC Package)
T
A
= 25°C
Symbol
V
OLP
V
OLV
V
IHD
V
ILD
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
Characteristic
Typ
0.3
−0.3
Max
0.5
−0.5
2.0
0.8
Unit
V
V
V
V
TEST POINT
A or B
50%
GND
t
PLH
O
t
PHL
V
CC
DEVICE
UNDER
TEST
OUTPUT
C
L
*
50% V
CC
*Includes all probe and jig capacitance
Figure 2. Switching Waveforms
Figure 3. Test Circuit
ORDERING INFORMATION
Device
MC74LVX00DR2G
MC74LVX00DTR2G
Package
SOIC−14 NB
(Pb−Free)
TSSOP−14*
Shipping
†
2500 Tape & Reel
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
http://onsemi.com
3
MC74LVX00
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G
ISSUE B
14X
K
REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0
_
8
_
0
_
8
_
0.10 (0.004)
0.15 (0.006) T U
S
M
T U
S
V
S
N
2X
L/2
14
8
0.25 (0.010)
M
L
PIN 1
IDENT.
1
7
B
−U−
N
F
DETAIL E
K
0.15 (0.006) T U
S
J J1
SECTION N−N
−W−
C
0.10 (0.004)
−T−
SEATING
PLANE
D
G
H
DETAIL E
SOLDERING FOOTPRINT*
7.06
1
14X
0.36
14X
1.26
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
4
ÇÇÇ
ÉÉÉ
ÇÇÇ
ÉÉÉ
ÇÇÇ
A
−V−
K1
0.65
PITCH
DIMENSIONS: MILLIMETERS
MC74LVX00
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE K
D
14
A
B
8
A3
H
1
7
E
L
DETAIL A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0
_
7
_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0
_
7
_
0.25
M
B
M
13X
b
0.25
M
C A
A
S
B
S
X 45
_
h
DETAIL A
e
A1
C
SEATING
PLANE
M
SOLDERING FOOTPRINT*
6.50
1
14X
1.18
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
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