Revision 3.1
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Copyright 2001Hynix Semiconductor Inc.
Revision Jun. 29, 2001.
Table of Contents
i
Table of Contents
0. Overview
0.1 GMS30C2216/32 RISC/DSP.............................................................................. 0-1
0.2 Block Diagram.................................................................................................... 0-8
0.3 Pin Configuration................................................................................................ 0-9
0.3.1 GMS30C2232, 160-Pin MQFP-Package - View from Top Side ........ 0-9
0.3.2 Pin Cross Reference by Pin Name .................................................... 0-10
0.3.2 Pin Cross Reference by Location ...................................................... 0-11
0.3.4 Pin Fuction ........................................................................................ 0-12
1. Architecture
1.1 Introduction...................................................................................................... 1-1
1.1.1 RISC Architecture ............................................................................... 1-1
1.1.2 Techniques to reduce CPI (Cycles per Instruction)............................. 1-2
1.1.3 The pipeline structure of GMS30C2232 ............................................. 1-7
1.2 Global Register Set .......................................................................................... 1-8
1.2.1 Program Counter PC, G0 .................................................................... 1-9
1.2.2 Status Register SR, G1 ...................................................................... 1-10
1.2.3 Floating-Point Exception Register FER, G2 ..................................... 1-13
1.2.4 Stack Pointer SP, G18 ....................................................................... 1-14
1.2.5 Upper Stack Bound UB, G19 ............................................................ 1-14
1.2.6 Bus Control Register BCR, G20 ....................................................... 1-14
1.2.7 Timer Prescaler Register TPR, G21 .................................................. 1-15
1.2.8 Timer Compare Register TCR, G22.................................................. 1-15
1.2.9 Timer Register TR, G23.................................................................... 1-15
1.2.10 Watchdog Compare Register WCR, G24........................................ 1-15
1.2.11 Input Status Register ISR, G25 ....................................................... 1-15
1.2.12 Function Control Register FCR, G26.............................................. 1-15
1.2.13 Memory Control Register MCR, G27............................................. 1-16
1.3 Local Register Set.......................................................................................... 1-16
1.4 Privilege States .............................................................................................. 1-17
1.5 Register Data Types....................................................................................... 1-18
1.6 Memory Organization.................................................................................... 1-19
1.7 Stack............................................................................................................... 1-21
1.8 Instruction Cache ........................................................................................... 1-26
1.9 On-Chip Memory (IRAM)............................................................................. 1-29
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