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MC74ACT299NG

Description
Counter Shift Registers 4.5-5.5V 8-Input Universal Shift
Categorylogic    logic   
File Size255KB,11 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
Environmental Compliance
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MC74ACT299NG Overview

Counter Shift Registers 4.5-5.5V 8-Input Universal Shift

MC74ACT299NG Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerON Semiconductor
Parts packaging codeDIP
package instructionDIP, DIP20,.3
Contacts20
Reach Compliance Codeunknown
Other featuresSISO OPERATION ALSO AVAILABLE
Counting directionBIDIRECTIONAL
seriesACT
JESD-30 codeR-PDIP-T20
JESD-609 codee3
length26.415 mm
Logic integrated circuit typePARALLEL IN PARALLEL OUT
Maximum Frequency@Nom-Sup110000000 Hz
Number of digits8
Number of functions1
Number of terminals20
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP20,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
propagation delay (tpd)16.5 ns
Certification statusNot Qualified
Maximum seat height4.57 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin (Sn)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width7.62 mm
minfmax110 MHz
Base Number Matches1
MC74AC299, MC74ACT299
8−Input Universal Shift/
Storage Register with
Common Parallel I/O Pins
The MC74AC299/74ACT299 is an 8−bit universal shift/storage
register with 3−state outputs. Four modes of operation are possible:
hold (store), shift left, shift right and load data. The parallel load inputs
and flip−flop outputs are multiplexed to reduce the total number of
package pins. Additional outputs are provided for flip−flops Q
0
, Q
7
to
allow easy serial cascading. A separate active LOW Master Reset is
used to reset the register.
http://onsemi.com
w
PDIP−20
N SUFFIX
CASE 738
20
1
Common Parallel I/O for Reduced Pin Count
Additional Serial Inputs and Outputs for Expansion
Four Operating Modes: Shift Left, Shift Right, Load and Store
3−State Outputs for Bus−Oriented Applications
Outputs Source/Sink 24 mA
′ACT299
Has TTL Compatible Inputs
These devices are available in Pb−free package(s). Specifications herein
apply to both standard and Pb−free devices. Please see our website at
www.onsemi.com for specific Pb−free orderable part numbers, or
contact your local ON Semiconductor sales office or representative.
V
CC
20
S
1
19
DS
7
18
Q
7
17
I/O
7
16
I/O
5
15
I/O
3
14
I/O
1
13
CP
12
DS
0
11
20
1
SO−20
DW SUFFIX
CASE 751
ORDERING INFORMATION
Device
MC74AC299N
MC74ACT299N
MC74AC299DW
MC74AC299DWR2
MC74ACT299DW
Package
PDIP−20
PDIP−20
SOIC−20
SOIC−20
SOIC−20
SOIC−20
Shipping
18 Units/Rail
18 Units/Rail
38 Units/Rail
1000 Tape & Reel
38 Units/Rail
1000 Tape & Reel
1
S
0
2
OE
1
3
OE
2
4
I/O
6
5
I/O
4
6
I/O
2
7
I/O
0
8
Q
0
9
MR
10
GND
MC74ACT299DWR2
Figure 1. Pinout: 20−Lead Packages Conductors
(Top View)
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 9 of this data sheet.
PIN ASSIGNMENT
PIN
CP
DS
0
DS
7
S
0
, S
1
MR
OE
1
, OE
2
I/O
0
−I/O
7
Q
0
, Q
7
FUNCTION
Clock Pulse Input
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Asynchronous Master Reset
3−State Output Enable Inputs
Parallel Data Inputs or 3−State Parallel Outputs
Serial Outputs
©
Semiconductor Components Industries, LLC, 2006
June, 2006
Rev. 8
1
Publication Order Number:
MC74AC299/D

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MC74ACT299NG MC74ACT299DWG MC74ACT299N
Description Counter Shift Registers 4.5-5.5V 8-Input Universal Shift Counter Shift Registers 4.5-5.5V 8-Input Universal Shift Counter Shift Registers 4.5-5.5V 8-Input
Is it Rohs certified? conform to conform to incompatible
Maker ON Semiconductor ON Semiconductor ON Semiconductor
Parts packaging code DIP SOIC DIP
package instruction DIP, DIP20,.3 SOP, SOP20,.4 DIP, DIP20,.3
Contacts 20 20 20
Reach Compliance Code unknown unknown not_compliant
Other features SISO OPERATION ALSO AVAILABLE SISO OPERATION ALSO AVAILABLE SISO OPERATION ALSO AVAILABLE
Counting direction BIDIRECTIONAL BIDIRECTIONAL BIDIRECTIONAL
series ACT ACT ACT
JESD-30 code R-PDIP-T20 R-PDSO-G20 R-PDIP-T20
JESD-609 code e3 e3 e0
length 26.415 mm 12.8 mm 26.415 mm
Logic integrated circuit type PARALLEL IN PARALLEL OUT PARALLEL IN PARALLEL OUT PARALLEL IN PARALLEL OUT
Maximum Frequency@Nom-Sup 110000000 Hz 110000000 Hz 110000000 Hz
Number of digits 8 8 8
Number of functions 1 1 1
Number of terminals 20 20 20
Maximum operating temperature 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C
Output characteristics 3-STATE 3-STATE 3-STATE
Output polarity TRUE TRUE TRUE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code DIP SOP DIP
Encapsulate equivalent code DIP20,.3 SOP20,.4 DIP20,.3
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form IN-LINE SMALL OUTLINE IN-LINE
Peak Reflow Temperature (Celsius) NOT SPECIFIED 260 NOT SPECIFIED
power supply 5 V 5 V 5 V
propagation delay (tpd) 16.5 ns 16.5 ns 16.5 ns
Certification status Not Qualified Not Qualified Not Qualified
Maximum seat height 4.57 mm 2.65 mm 4.57 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V 5.5 V
Minimum supply voltage (Vsup) 4.5 V 4.5 V 4.5 V
Nominal supply voltage (Vsup) 5 V 5 V 5 V
surface mount NO YES NO
technology CMOS CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal surface Tin (Sn) Tin (Sn) Tin/Lead (Sn/Pb)
Terminal form THROUGH-HOLE GULL WING THROUGH-HOLE
Terminal pitch 2.54 mm 1.27 mm 2.54 mm
Terminal location DUAL DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED 40 NOT SPECIFIED
Trigger type POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE
width 7.62 mm 7.5 mm 7.62 mm
minfmax 110 MHz 110 MHz 110 MHz
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