MC74VHCT50A
Noninverting Buffer /
CMOS Logic Level Shifter
with LSTTL−Compatible Inputs
The MC74VHCT50A is a hex noninverting buffer fabricated with
silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS
low power dissipation.
The internal circuit is composed of three stages, including a buffered
output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and
the output has a full 5 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logic−level translator from
3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic
to 3.0 V CMOS Logic while operating at the high−voltage power
supply.
The MC74VHCT50A input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHCT50A to be used to interface 5 V circuits to 3 V
circuits. The output structures also provide protection when
V
CC
= 0 V. These input and output structures help prevent device
destruction caused by supply voltage
−
input/output voltage mismatch,
battery backup, hot insertion, etc.
Features
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14−LEAD SOIC
D SUFFIX
CASE 751A
14−LEAD TSSOP
DT SUFFIX
CASE 948G
PIN CONNECTION AND
MARKING DIAGRAM
(Top View)
V
CC
14
A6
13
Y6
12
A5
11
Y5
10
A4
9
Y4
8
1
A1
2
Y1
3
A2
4
Y2
5
A3
6
Y3
7
GND
•
•
•
•
•
•
High Speed: t
PD
= 3.5 ns (Typ) at V
CC
= 5 V
Low Power Dissipation: I
CC
= 2
mA
(Max) at T
A
= 25°C
TTL−Compatible Inputs: V
IL
= 0.8 V; V
IH
= 2.0 V
CMOS−Compatible Outputs: V
OH
> 0.8 V
CC
; V
OL
< 0.1 V
CC
@Load
Power Down Protection Provided on Inputs and Outputs
These Devices are Pb−Free and are RoHS Compliant
LOGIC DIAGRAM
A1
1
2
Y1
A1
A2
3
4
Y2
A2
A3
5
6
Y3
Y=A
A4
9
8
Y4
A4
A5
Y5
A6
A6
13
12
Y6
1
Y6
A3
1
1
1
1
1
Y1
Y2
Y3
Y4
Y5
For detailed package marking information, see the Marking
Diagram section on page 4 of this data sheet.
FUNCTION TABLE
A Input
L
H
Y Output
L
H
LOGIC SYMBOL
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
A5
11
10
©
Semiconductor Components Industries, LLC, 2013
October, 2013
−
Rev. 8
1
Publication Order Number:
MC74VHCT50A/D
MC74VHCT50A
MAXIMUM RATINGS
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
T
L
T
J
q
JA
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance
(Note 1)
SOIC
TSSOP
SOIC
TSSOP
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
Above V
CC
and Below GND at 85_C (Note 5)
Output in HIGH or LOW State
Parameter
Value
*0.5
to
)7.0
*0.5 v
V
I
v )7.0
*0.5 v
V
O
v )7.0
*20
$20
$25
$50
$50
*65
to
)150
260
)150
125
170
500
450
> 2000
> 200
2000
$300
Unit
V
V
V
mA
mA
mA
mA
mA
_C
_C
_C
_C/W
P
D
Power Dissipation in Still Air
mW
V
ESD
ESD Withstand Voltage
V
I
Latch−Up
Latch−Up Performance
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Characteristics
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V
CC
= 0
High or Low State
Symbol
V
CC
V
IN
V
OUT
T
A
t
r
, t
f
Min
2.0
0.0
0.0
0.0
−55
0
0
Max
5.5
5.5
5.5
V
CC
+125
100
20
TEST POINT
3.0V
A
50%
GND
t
PLH
t
PHL
V
OH
Y
50% V
CC
V
OL
*Includes all probe and jig capacitance
OUTPUT
DEVICE
UNDER
TEST
C
L
*
Unit
V
V
V
°C
ns/V
Operating Temperature Range
Input Rise and Fall Time
V
CC
= 3.3 V
±
0.3 V
V
CC
= 5.0 V
±
0.5 V
Figure 1. Switching Waveforms
Figure 2. Test Circuit
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2
MC74VHCT50A
DC ELECTRICAL CHARACTERISTICS
V
CC
Symbol
V
IH
Parameter
Minimum High−Level
Input Voltage
Maximum Low−Level
Input Voltage
Minimum High−Level
Output Voltage
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OH
=
−50
mA
V
IN
= V
IH
or V
IL
I
OH
=
−4
mA
I
OH
=
−8
mA
V
IN
= V
IH
or V
IL
I
OL
= 50
mA
V
IN
= V
IH
or V
IL
I
OH
=
−4
mA
I
OL
= 8 mA
V
IN
= 5.5 V or GND
V
IN
= V
CC
or GND
Input: V
IN
= 3.4 V
V
OUT
= 5.5 V
Test Conditions
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
3.0
4.5
3.0
4.5
3.0
4.5
0 to
5.5
5.5
5.5
0.0
2.9
4.4
2.58
3.94
0.0
0.0
0.1
0.1
0.36
0.36
±0.1
2.0
1.35
0.5
3.0
4.5
Min
1.2
2.0
2.0
0.53
0.8
0.8
2.9
4.4
2.48
3.80
0.1
0.1
0.44
0.44
±1.0
20
1.50
5.0
T
A
= 25°C
Typ
Max
T
A
≤
85°C
Min
1.2
2.0
2.0
0.53
0.8
0.8
2.9
4.4
2.34
3.66
0.1
0.1
0.52
0.52
±1.0
40
1.65
10
Max
T
A
≤
125°C
Min
1.2
2.0
2.0
0.53
0.8
0.8
Max
Unit
V
V
IL
V
V
OH
V
V
V
OL
Maximum Low−Level
Output Voltage
V
IN
= V
IH
or V
IL
V
V
I
IN
I
CC
I
CCT
I
OFF
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
Quiescent Supply
Current
Output Leakage
Current
μA
μA
mA
μA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS
(C
load
= 50 pF, Input t
r
= t
f
= 3.0ns)
Symbol
Parameter
Test Conditions
Min
T
A
= 25°C
Typ
5.5
8.0
6.2
7.0
5
T
A
≤
85°C
T
A
≤
125°C
Max
7.9
11.4
7.5
8.5
10
Min
1.0
1.0
Max
Min
Max
Unit
ns
t
PLH
,
t
PHL
Maximum
Propogation Delay,
Input A to Y
V
CC
= 3.3
±
0.3 V
V
CC
= 5.0
±
0.5 V
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
9.5
13.0
8.5
9.5
10
9.5
10.5
10
pF
C
IN
Maximum Input
Capacitance
Typical @ 25°C, V
CC
= 5.0 V
15
C
PD
Power Dissipation Capacitance (Note 6)
pF
6. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
. C
PD
is used to determine the no−load dynamic
power consumption; P
D
= C
PD
V
CC2
f
in
+ I
CC
V
CC
.
NOISE CHARACTERISTICS
(Input t
r
= t
f
= 3.0ns, C
L
= 50pF, V
CC
= 5.0V)
T
A
= 25°C
Symbol
V
OLP
V
OLV
V
IHD
V
ILD
Characteristic
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
Typ
0.8
−0.8
Max
1.0
−1.0
2.0
0.8
Unit
V
V
V
V
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3
MC74VHCT50A
ORDERING INFORMATION
Device
MC74VHCT50ADG
MC74VHCT50ADR2G
MC74VHCT50ADTG
MC74VHCT50ADTR2G
Package
SOIC−14
(Pb−Free)
SOIC−14
(Pb−Free)
TSSOP−14
(Pb−Free)
TSSOP−14
(Pb−Free)
Shipping
†
55 Units / Rail
2500 / Tape & Reel
96 Units / Rail
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MARKING DIAGRAMS
(Top View)
14
13
12
11
10
9
8
14 13 12 11 10
VHCT
50A
ALYWG
G
5
6
7
1
2
3
4
5
6
7
9
8
VHCT50AG
AWLYWW*
1
2
3
4
14−LEAD SOIC
D SUFFIX
CASE 751A
A
WL, L
Y
WW, W
G or
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
14−LEAD TSSOP
DT SUFFIX
CASE 948G
*See Applications Note #AND8004/D for date code and traceability information.
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4
MC74VHCT50A
PACKAGE DIMENSIONS
SOIC−14 NB
D SUFFIX
CASE 751A−03
ISSUE K
D
14
8
A
B
A3
E
L
H
1
7
DETAIL A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0
_
7
_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0
_
7
_
0.25
M
B
M
13X
b
0.25
M
C A
A
S
B
S
X 45
_
h
DETAIL A
e
A1
C
M
SEATING
PLANE
SOLDERING FOOTPRINT*
6.50
1
14X
1.18
1.27
PITCH
0.58
14X
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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