XR18910
8:1 Sensor Interface Analog Front End
Description
The
XR18910
is a unique sensor interface integrated circuit with an
onboard 8:1 multiplexer, offset correction Digital-to-Analog Converter
(DAC), instrumentation amplifier and voltage reference. The XR18910
is designed to integrate multiple bridge sensors with a Microcontroller
(MCU) or Field-Programmable Gate Array (FPGA).
The integrated offset correction DAC provides digital calibration of the
variable and in many cases substantial offset voltage generated by the
bridge sensors. The DAC is controlled by an I
2
C compatible 2-wire serial
interface. The serial interface also provides the user with easy controls
to the XR18910’s many functions such as input and gain selection.
A linear regulator (LDO) provides a regulated voltage to power the input
bridge sensors and is selectable, between 3V and 2.65V. The LDO
current can be sensed and a proportional voltage present at the output
of the IC for monitoring the LDO current.
The XR18910 offers 8 fixed gain settings (from 2V/V to 760V/V), each
with an error of only ±0.5%, that are selectable via the I
2
C interface.
It also offers less than 3mV maximum input offset voltage, 100pA
maximum input bias current, and 100pA maximum input offset current.
The XR18910 is designed to operate from 2.7V to 5V supplies, specified
over the industrial temperature range of -40°C to 85°C and is offered in
a space saving 3.5mm x 3.5mm QFN package. It consumes less than
559μA supply current and offers a sleep mode for added power savings.
The XR18910 is well suited for industrial and consumer applications
using bridge sensors.
FEATURES
■■
Integrated features for interfacing multiple
bridge sensors with an MCU or FPGA
8:1 differential MUX with I
2
C interface
Instrumentation amplifier
LDO
Offset correction DAC with I
2
C interface
(±560mV offset correction range)
■
■
Eight selectable voltage gains from 2V/V to
760V/V with only ±0.5% gain error
■
■
3mV maximum input offset voltage
■
■
100pA maximum input bias current
■
■
559μA maximum supply current
■
■
2.7V to 5V analog supply voltage range
■
■
1.8V to 5V digital supply voltage range
■
■
-40°C to 85°C temperature range
■
■
3.5mm x 3.5mm QFN-24 package
APPLICATIONS
■
■
Bridge sensor interface
■
■
Pressure and temperature sensors
■
■
Strain gauge amplifier
■
■
Industrial process controls
■
■
Weigh scales
Typical Application
V
CC
6.8 F
+
V
DD
6.8 F
+
0.1 F
BRDG
BRIDGE 8
VCC
0.1 F
VDD
2.5
2
0.1 F
1.5
RTI Noise (µV)
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
0
2
4
6
Time (seconds)
8
10
LDO
IN8+
IN8-
INA /
PGA
8:1
MUX
BRIDGE 1
IN1+
IN1-
OUT
10k
10nF
ADC
µC
±560mV
OFFSET TRIM
10-BIT
DAC
V
DD
PGA
SDA
V
DD
4.7k
4.7k
I
2
C
CONTROL
SCL
XR18910
AGND
DGND
Figure 1. Typical Application
REV1A
Figure 2. 0.1Hz to 10Hz RTI Voltage Noise
1/19
XR
18910
Absolute Maximum Ratings
Stresses beyond the limits listed below may cause
permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect
device reliability and lifetime.
Analog supply voltage (V
CC)
.......................................... 0V to 5.5V
Digital supply voltage (V
DD
) ........................................... 0V to 5.5V
Digital input/output (V
DDIO
) ............................................ 0V to 5.5V
V
IN
.....................................................................................0 to V
CC
Differential input voltage (current limit of 10mA) ...................... V
CC
ESD rating (HBM - human body model) ...................................4kV
Operating Conditions
Analog supply voltage range .................................... 2.7V to 5.25V
Digital supply voltage range.......................................1.7V to 5.25V
Operating temperature range ...................................-40°C to 85°C
Junction temperature ............................................................ 150°C
Storage temperature range .....................................-65°C to 150°C
Lead temperature (soldering, 10s) ........................................260°C
Package thermal resistance
θ
JA
......................................50°C/W
(1)
NOTE:
1. JEDEC standard, multi-layer test boards, still air.
REV1A
2/19
XR
18910
Electrical Characteristics
T
A
= 25°C, V
CC
= 3.3V, V
DD
= 1.8V, R
L
= 10kΩ to 1.5V, G = 760, unless otherwise noted.
Symbol
V
IO
d
VIO
I
B
I
OS
PSRR
Parameter
Input offset voltage
Input offset voltage average drift
Input bias current
Input offset current
Power supply rejection ratio
Gain = 2
Gain = 20
Gain = 40
Gain = 80
Gain = 150
Gain = 300
Gain = 600
Gain = 760
Conditions
Input referred
Min
-3
-100
-100
Typ
±0.02
3
15
1
91
2.0
20.0
40.0
80.0
150.0
299.9
599.6
759.4
Max
3
100
100
Units
mV
μV/°C
pA
pA
dB
V/V
V/V
V/V
V/V
V/V
V/V
V/V
V/V
DC Performance
V
CC
= 2.7V to 5V
60
G
Nominal, refer to Gain Register Table (pg. 7)
G
E
I
SVCC
I
SVCCD
I
SVDD
I
STOTAL
I
SDTOTAL
Gain error
Gain error vs temperature
V
CC
supply current
Disable V
CC
supply current
V
DD
supply current
Total supply current
Total disable supply current
No load to output, no load to LDO
No load to output, no load to LDO
No load to output, no load to LDO, I
2
C running
No load to output, no load to LDO
No load to output, no load to LDO, LDO DIS
No load to output, no load to LDO, LDO EN
-0.5
±10
435
48
22
457
45
70
10
13
|| 11.2
0.5
Input referred, V
CM
= 0.5 to 2.0V
R
L
= 10kΩ to 1.5V
Offset DAC 0 00 0000 0000, G = 2
RTI (referred to input)
75
0.1
1.4
±560
8
1.5k load, LDO bit LOW
1.5k load, LDO bit HIGH
V
CC
= 2.8V, LDO = 2.65V, I
LOAD
= 10mA
10
Output referred, V
CC
= 3V to 5V, LDO = 2.65V
Output referred, V
CC
= 3.3V to 5V, LDO = 3V
Output voltage relative to 1.5V / LDO current, G = 2
G=2
45
45
0.08
25
63
63
0.1
18.8
-6%
-6%
10
3
2.65
0.23 to
3.06
88
0.04 to
3.29
1.5
0.5
530
62
29
559
91
%
ppm/°C
μA
μA
μA
μA
μA
μA
Ω || pF
Input Characteristics
Input impedance
CMIR
CMRR
V
OUT
V
OO
Offset DAC
Offset DAC range
Offset monotonicity
LDO
Output voltage
Dropout voltage
Output current
Power supply rejection ratio
Output current sense transimpedance slope
Output current sense range clip
+6%
+6%
150
V
V
mV
mA
dB
dB
0.12
V/mA
mA
mV
Bits
Common mode input range
Common mode rejection ratio
Output voltage swing
Output offset
2.5
V
dB
Output Characteristics
3.1
1.6
V
V
REV1A
3/19
XR
18910
Electrical Characteristics (Continued)
T
A
= 25°C, V
CC
= 3.3V, V
DD
= 1.8V, R
L
= 10kΩ to 1.5V, G = 760, unless otherwise noted.
Symbol
Parameter
Conditions
G = 760
G=2
V
OUT
= 1V
P-P
, G = 2
f = 10Hz
e
NI
i
N
e
NP-P
XTALK
T
S
T
WAKE
Input voltage noise, RTI
Input current noise
Peak-to-peak noise
Crosstalk
Set-up time, 1% settling
Wake up time, 1% settling
f = 100Hz
f = 1kHz
f = 10Hz
f = 0.1 to 10Hz
Channel-to-channel, f = 1kHz
Analog ready after serial register finished write
Wake from ACK of SLEEP_OUT command
Min
Typ
66
1300
1
75
46
35
0.6
2
90
3.5
9.6
Max
Units
kHz
kHz
V/μs
nV/√Hz
nV/√Hz
nV/√Hz
fA/√Hz
μV
P-P
dB
μs
μs
Dynamic Performance
BW
SR
-3dB bandwidth
Slew rate
Digital Characteristics (CMOS)
Symbol
V
IH
V
IL
I
IH
I
IL
CLK
F
Parameter
Logic input HIGH
Logic input LOW
Input leakage HIGH
Input leakage LOW
Clock rate
Conditions
Min
0.7
x
V
DD
0
Typ
Max
V
DD
0.3
x
V
DD
10
Units
V
V
μA
μA
MHz
V
I
= V
S
V
I
= 0
-10
0.4
I
2
C Bus Timing
T
A
= -40 to 85°C, V
DD
= 1.8 to 5V, unless otherwise noted.
Standard Mode
I
2
C-BUS
Min
f
SCL
T
BUF
T
HD;STA
T
SU;STA
T
HD;DAT
T
VD;ACK
T
VD;DAT
T
SU;DAT
T
LOW
T
HIGH
T
F
T
R
T
SP
Operating frequency
Bus free time between STOP and
START
START condition hold time
START condition setup time
Data hold time
Data valid acknowledge
SCL LOW to data out valid
Data setup time
Clock LOW period
Clock HIGH period
Clock/data fall time
Clock/data rise time
Pulse width of spikes tolerance
0.5
250
4.7
4.0
300
1000
0.5
0
4.7
4.0
4.7
0
0.6
0.6
150
1.3
0.6
300
300
Symbol
Parameter
Fast Mode
I
2
C-BUS
Min
0
1.3
0.6
0.6
0
0.6
0.6
Units
kHz
μs
μs
μs
μs
μs
ns
ns
μs
μs
ns
ns
μs
Max
100
Max
400
REV1A
4/19
REV. 1.0.0
XR20M1280
XR
SHIFTERS
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL
18910
Electrical Characteristics (Continued)
F
IGURE
22. I
2
C-B
US
T
IMING
D
IAGRAM
START
condition
(S)
T
SU;STA
Bit 7
MSB
(A7)
T
LOW
T
HIGH
Bit 6
(A6)
Bit 0
LSB
(R/W)
Acknowledge
(A)
STOP
condition
(P)
Protocol
1/F
SCL
SCL
T
F
T
SP
T
BUF
T
R
SDA
T
HD;STA
T
SU;DAT
T
HD;DAT
T
VD;DAT
T
VD;ACK
T
SU;STO
Figure 3. I
2
C Bus Timing Diagram
F
IGURE
23. W
RITE
T
O
O
UTPUT
SLAVE
ADDRESS
SDA
W
A
GPIOLVL REG.
A
DATA
A
T
D1
GPIOn
REV1A
5/19