NPIC6C596PW-Q100 datasheet, PDF

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NPIC6C596PW-Q100: DescriptionCounter Shift Registers 8 Bit Shift Reg 5.5V; Categorysemiconductor logic; File Size2MB，21 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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NPIC6C596PW-Q100 Overview

Counter Shift Registers 8 Bit Shift Reg 5.5V

NPIC6C596PW-Q100 Parametric

Parameter Name	Attribute value
Product Category	Counter Shift Registers
Manufacturer	NXP
RoHS	Details
Package / Case	TSSOP-16
Logic Family	NPIC
Logic Type	Shift Register
Output Type	Open Drain
Propagation Delay Time	5 ns
Supply Voltage - Max	5.5 V
Minimum Operating Temperature	- 40 C
Maximum Operating Temperature	+ 125 C
Packaging	Reel
Function	8 Bit Shift Register
Mounting Style	SMD/SMT
Operating Supply Voltage	4.5 V to 5.5 V
Reset Type	Asynchronous
Factory Pack Quantity	2500
Supply Voltage - Min	4.5 V
Timing Type	Asynchronous
Unit Weight	0.006102 oz

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NPIC6C596-Q100

Power logic 8-bit shift register; open-drain outputs

Rev. 2 — 4 July 2013

Product data sheet

1. General description

The NPIC6C596-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage

The device features a serial input (DS) and a serial output (Q7S) to enable cascading and

an asynchronous reset MR input. A LOW on MR resets both the shift register and storage

the shift register is transferred to the storage register on a LOW-to-HIGH transition of the

STCP input. If both clocks are connected together, the shift register is always one clock

pulse ahead of the storage register. To provide additional hold time in cascaded

applications, the serial output QS7 is clocked out on the falling edge of SHCP. Data in the

storage register drives the gate of the output extended-drain NMOS (EDNMOS) transistor

whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to

assume a high-impedance OFF-state. Operation of the OE input does not affect the state

of the registers.

The open-drain outputs are 33 V/100 mA continuous current extended-drain NMOS

transistors designed for use in systems that require moderate load power such as LEDs.

Integrated voltage clamps in the outputs provide protection against inductive transients

making the device suitable for power driver applications such as relays, solenoids and

other low-current or medium-voltage loads.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits



Automotive product qualification in accordance with AEC-Q100 (Grade 1)



Specified from

40 C

to +125

C



Low R

DSon



Eight Power EDNMOS transistor outputs of 100 mA continuous current



250 mA current limit capability



Output clamping voltage 33 V



30 mJ avalanche energy capability



Enhanced cascading for multiple stages



All registers cleared with single input



Low power consumption



ESD protection:



HBM AEC-Q100-002 revision D exceeds 2500 V



CDM AEC-Q100-011 revision B exceeds 1000 V

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