Data Sheet
FEATURES
Low Power, Precision Analog Microcontroller,
Dual Sigma-Delta ADCs, Flash/EE, ARM7TDMI
ADuC7060/ADuC7061
Packages and temperature range
Fully specified for −40°C to +125°C operation
32-lead LFCSP (5 mm × 5 mm)
48-lead LFCSP and LQFP
Derivatives
32-lead LFCSP (ADuC7061)
48-lead LQFP and 48-lead LFCSP (ADuC7060)
Analog input/output
Dual (24-bit) ADCs
Single-ended and differential inputs
Programmable ADC output rate (4 Hz to 8 kHz)
Programmable digital filters
Built-in system calibration
Low power operation mode
Primary (24-bit) ADC channel
2 differential pairs or 4 single-ended channels
PGA (1 to 512) input stage
Selectable input range: ±2.34 mV to ±1.2 V
30 nV rms noise
Auxiliary (24-bit) ADC: 4 differential pairs or 7 single-
ended channels
On-chip precision reference (±10 ppm/°C)
Programmable sensor excitation current sources
200 μA to 2 mA current source range
Single 14-bit voltage output DAC
Microcontroller
ARM7TDMI core, 16-/32-bit RISC architecture
JTAG port supports code download and debug
Multiple clocking options
Memory
32 kB (16 kB × 16) Flash/EE memory, including 2 kB kernel
4 kB (1 kB × 32) SRAM
Tools
In-circuit download, JTAG based debug
Low cost, QuickStart™ development system
Communications interfaces
SPI interface (5 Mbps)
4-byte receive and transmit FIFOs
UART serial I/O and I
2
C (master/slave)
On-chip peripherals
4× general-purpose (capture) timers including
Wake-up timer
Watchdog timer
Vectored interrupt controller for FIQ and IRQ
8 priority levels for each interrupt type
Interrupt on edge or level external pin inputs
16-bit, 6-channel PWM
General-purpose inputs/outputs
Up to 14 GPIO pins that are fully 3.3 V compliant
Power
AVDD/DVDD specified for 2.5 V (±5%)
Active mode: 2.74 mA (@ 640 kHz, ADC0 active)
10 mA (@ 10.24 MHz, both ADCs active)
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
APPLICATIONS
Industrial automation and process control
Intelligent, precision sensing systems, 4 mA to 20 mA
loop-based smart sensors
GENERAL DESCRIPTION
The
ADuC7060/ADuC7061
series are fully integrated, 8 kSPS,
24-bit data acquisition systems incorporating high performance
multichannel sigma-delta (Σ-Δ) analog-to-digital converters
(ADCs), 16-bit/ 32-bit ARM7TDMI® MCU, and Flash/EE memory
on a single chip.
The ADCs consist of a primary ADC with two differential pairs or
four single-ended channels and an auxiliary ADC with up to seven
channels. The ADCs operate in single-ended or differential input
mode. A single-channel buffered voltage output DAC is available
on chip. The DAC output range is programmable to one of four
voltage ranges.
The devices operate from an on-chip oscillator and a PLL gene-
rating an internal high frequency clock up to 10.24 MHz. The
microcontroller core is an ARM7TDMI, 16-bit/32-bit RISC
machine offering up to 10 MIPS peak performance; 4 kB of SRAM
and 32 kB of nonvolatile Flash/EE memory are provided on chip.
The ARM7TDMI core views all memory and registers as a single
linear array.
The
ADuC7060/ADuC7061
contains four timers. Timer1 is a
wake-up timer with the ability to bring the part out of power saving
mode. Timer2 is configurable as a watchdog timer. A 16-bit PWM
with six output channels is also provided. The
ADuC7060/
ADuC7061
contains an advanced interrupt controller. The
vectored interrupt controller (VIC) allows every interrupt to be
assigned a priority level. It also supports nested interrupts to a
maximum level of eight per IRQ and FIQ. When IRQ and FIQ
interrupt sources are combined, a total of 16 nested interrupt levels
is supported. On-chip factory firmware supports in-circuit serial
download via the UART serial interface ports and nonintrusive
emulation via the JTAG interface. The parts operate from 2.375 V
to 2.625 V over an industrial temperature range of −40°C to
+125°C.
Rev. F
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ADuC7060/ADuC7061
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 3
Functional Block Diagram .............................................................. 5
Specifications..................................................................................... 6
Electrical Specifications ............................................................... 6
Timing Specifications ................................................................ 11
Absolute Maximum Ratings.......................................................... 15
ESD Caution ................................................................................ 15
Pin Configurations and Function Descriptions ......................... 16
Terminology .................................................................................... 21
Overview of the ARM7TDMI Core ............................................. 22
Thumb Mode (T)........................................................................ 22
Multiplier (M) ............................................................................. 22
EmbeddedICE (I) ....................................................................... 22
ARM Registers ............................................................................ 22
Interrupt Latency ........................................................................ 23
Memory Organization ............................................................... 23
Flash/EE Control Interface........................................................ 24
Memory Mapped Registers ....................................................... 28
Complete MMR Listing ............................................................. 29
Reset ............................................................................................. 34
Oscillator, PLL, and Power Control ............................................. 35
Clocking System ......................................................................... 35
Power Control System................................................................ 35
ADC Circuit Information .............................................................. 39
Reference Sources ....................................................................... 40
Diagnostic Current Sources ...................................................... 40
Sinc3 Filter ................................................................................... 41
ADC Chopping ........................................................................... 41
Programmable Gain Amplifier ................................................. 41
Excitation Sources ...................................................................... 41
ADC Low Power Mode.............................................................. 41
ADC Comparator and Accumulator ....................................... 42
Temperature Sensor ................................................................... 42
ADC MMR Interface ................................................................. 42
Example Application Circuits ................................................... 55
DAC Peripherals ............................................................................. 57
DAC .............................................................................................. 57
Data Sheet
MMR Interface ........................................................................... 57
Using the DAC ............................................................................ 58
Nonvolatile Flash/EE Memory ..................................................... 59
Flash/EE Memory Reliability .................................................... 59
Programming .............................................................................. 59
Processor Reference Peripherals................................................... 60
Interrupt System ......................................................................... 60
IRQ ............................................................................................... 60
Fast Interrupt Request (FIQ) .................................................... 61
Programmed Interrupts............................................................. 62
Vectored Interrupt Controller (VIC) ....................................... 62
VIC MMRs .................................................................................. 62
Timers .............................................................................................. 67
HR:MIN:SEC: 1/128 Format .................................................... 67
Timer0.......................................................................................... 68
Timer1 or Wake-Up Timer ....................................................... 70
Timer2 or Watchdog Timer ...................................................... 72
Timer3.......................................................................................... 74
Pulse-Width Modulator................................................................. 76
Pulse-Width Modulator General Overview ........................... 76
UART Serial Interface .................................................................... 81
Baud Rate Generation ................................................................ 81
UART Register Definitions ....................................................... 81
I
2
C ..................................................................................................... 87
Configuring External Pins for I
2
C Functionality ................... 87
Serial Clock Generation ............................................................ 88
I
2
C Bus Addresses ....................................................................... 88
I
2
C Registers ................................................................................ 88
Serial Peripheral Interface ............................................................. 97
MISO (Master In, Slave Out) Pin ............................................. 97
MOSI (Master Out, Slave In) Pin ............................................. 97
SCLK (Serial Clock I/O) Pin..................................................... 97
Slave Select (P0.0/SS ) Input Pin ............................................... 97
E
Configuring External Pins for SPI Functionality ................... 97
SPI Registers ................................................................................ 98
General-Purpose I/O ................................................................... 102
GPxCON Registers................................................................... 102
GPxDAT Registers ................................................................... 103
GPxSET Registers ..................................................................... 103
GPxCLR Registers .................................................................... 103
Rev. F | Page 2 of 107
Data Sheet
GPxPAR Registers .................................................................... 103
Hardware Design Considerations .............................................. 105
Power Supplies .......................................................................... 105
ADuC7060/ADuC7061
Outline Dimensions ......................................................................106
Ordering Guide .........................................................................107
REVISION HISTORY
2/2017—Rev. E to Rev. F
Changed CP-32-4 to CP-32-11 .................................... Throughout
Changed CP-48-3 to CP-48-5 ...................................... Throughout
Changes to Table 5 ..........................................................................13
Changes to Table 6 ..........................................................................14
Changes to Serial Peripheral Interface .........................................97
Changes to Figure 30 and Figure 31 ...........................................106
Updated Outline Dimensions ......................................................106
Changes to Ordering Guide .........................................................107
10/2014—Rev. D to Rev. E
Changes to Table 1 ............................................................................ 6
Changed FEESIGN to FEESIG (Throughout).............................25
Changed FEEHIDE to FEEHID (Throughout) ..........................26
Changes to Table 36 ........................................................................40
Changes to Sinc3 Filter Section .....................................................41
Changes to Table 43 ........................................................................46
Changes to ADC Filter Register Section ......................................48
Changes to Table 94 ........................................................................85
Changes to I
2
C Section ...................................................................87
Changes to Table 97 ........................................................................89
Changed Register I2CMSTA, Bit 7 from I2CMNA to I2CMND;
Table 98 .............................................................................................90
Changes to Table 104. .....................................................................93
Changes to Table 105 ......................................................................94
Updated Figure 31, Outline Dimensions ...................................106
4/2012—Rev. C to Rev. D
Changes to Table 1 ............................................................................ 6
Changes to Table 7 ..........................................................................14
Changes to Table 16 ........................................................................25
Change to Command Sequence for Executing a Mass Erase
Section ...............................................................................................26
Changes to Table 19 ........................................................................29
Changes to Power and Clock Control Registers Section ...........35
Changes to Figure 20 ......................................................................55
Changes to Bit 5 in Table 63...........................................................57
Changes to Timers Section; Added Hr:Min:Sec: 1/128 Format
Section and Table 79, Renumbered Sequenitially .......................67
Changes to Timer1 or Wake-Up Timer Section .........................70
Changes to Timer2 Load Register Section and Timer2 Value
Register Section ...............................................................................71
Added Table 108 ..............................................................................98
Updated Outline Dimensions ......................................................105
5/2011—Rev. B to Rev. C
Change to Figure 1 ............................................................................ 4
Changes to Table 1 ............................................................................ 6
Add Temporary Protection Section and Keyed Permanent
Protection Section ........................................................................... 25
Added Permanent Protection Section and Sequence to Write the
Software Protection Key and Set Permanent Protection Section... 26
Changes to Power Control System Section.................................. 35
Changes to Bit 9:6, Table 43 ........................................................... 45
Changes to Primary Channel ADC Data Register Section and
Table 49 ............................................................................................. 50
Changes to IRQEN Section and IRQCLR Section ..................... 59
Changes to Timer1 or Wake-Up Timer Section ......................... 69
Changes to Table 108 ....................................................................101
2/2010—Rev. A to Rev. B
Changes to Features Section ............................................................ 1
Changes to Table 1 ............................................................................ 4
Changes to Digital I/O Voltage to DGND Parameter ................ 14
Changes to Pin 19, Pin 20, and Pin 45 Descriptions (Table 8).. 16
Changes to Pin 13, Pin 14, and Pin 29 Descriptions (Table 9).. 18
Changes to Bit 8 in Table 14 .......................................................... 23
Changes to Table 20 ........................................................................ 28
Changes to Power Control System Section.................................. 34
Added Table 32 ................................................................................ 35
Changes to Endnote 2 and Endnote 3 of Table 34 ...................... 36
Changes to Table 42 ........................................................................ 42
Changes to Bit 12 and Bits[3:0] in Table 43 ................................. 44
Changes to Bit 12 in Table 44 ........................................................ 45
Changes to Endnote 2 in Table 45 ................................................ 47
Changes to Bit 5 in Table 63 .......................................................... 55
Changes to Serial Downloading (In-Circuit Programming)
Section .............................................................................................. 57
Changes to Priority Registers Section .......................................... 61
Changes to GPxPAR Registers Section ...................................... 101
6/2009—Rev. 0 to Rev. A
Added ADuC7061.............................................................. Universal
Added New Package CP-32-4 ........................................... Universal
Changes to Features Section ............................................................ 1
Changes to General Description Section ....................................... 1
Changes to Figure 1 .......................................................................... 4
Changes to Table 1 ............................................................................ 7
Deleted Endnote to Table 2 ............................................................ 10
Changes to Endnotes, Table 3 and Table 4................................... 11
Changes to Endnotes, Table 5 ........................................................ 12
Changes to Endnotes, Table 6 ........................................................ 13
Changes to Figure 7 and Table 8 ................................................... 15
Added Figure 8 and Table 9, Renumbered Sequentially ............ 18
Changes to Flash EE/Control Interface Section.......................... 23
Change to Code 0x04 Description, Table 15 ............................... 24
Change to Bit 31 Description, Table 16 ........................................ 25
Rev. F | Page 3 of 107
ADuC7060/ADuC7061
Changes to Table 17 ........................................................................ 27
Changes to Table 19 T0CLRI and Table 20 ................................. 28
Changes to Endnote, Table 21 ....................................................... 29
Change to SPITX Default Value, Table 25 ................................... 30
Changes to External Clock Selection Section ............................. 33
Changes to ADC Circuit Information Section ........................... 36
Change to Column Heading Table 35 .......................................... 37
Change to Bit 6 Description, Table 39 ......................................... 40
Change to Bit 12 Description, Table 43 ....................................... 44
Changes to Primary Channel ADC Data Register Section
and Auxiliary Channel ADC Data Register Section .................. 48
Change to Table 59 and Figure 17 ................................................ 51
Changes to Using the DAC Section ............................................. 55
Changes to Nonvolatile Flash/EE Memory Section and
Programming Section .................................................................... 56
Changes to Vectored Interrupt Controller (VIC) Section ........ 59
Changes to Priority Registers Section .......................................... 60
Change to Table 73 ......................................................................... 61
Data Sheet
Changes to Figure 23...................................................................... 65
Changes Table 78 ............................................................................ 66
Changes to Figure 24 and Table 79 .............................................. 68
Changes to Timer2 Interface Section and Figure 25 ................. 69
Changes to Timer3 Capture Register Section............................. 71
Change to Bits[16:12] Description, Table 81 .............................. 72
Changes Pulse-Width Modulator General Overview Section,
Table 82, and Figure 26 .................................................................. 73
Changes to Table 84 Column Headings ...................................... 75
Changes to Table 92 ....................................................................... 82
Changes to Bit 1, Table 102 ........................................................... 90
Changes to Bit 11 Description, Table 105 ................................... 95
Changes to SPIMDE Bit Description, Table 106 ........................ 97
Updated Outline Dimensions ..................................................... 103
Changes to Ordering Guide ........................................................ 104
4/2009—Revision 0: Initial Version
Rev. F | Page 4 of 107
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
PRECISION ANALOG PERIPHERALS
ADC0
ADC1
POR
MUX
PGA
24-BIT
Σ-∆
ADC
ARM7TDMI
MCU
MUX
BUF
24-BIT
Σ-∆
ADC
10MHz
MEMORY
32kB FLASH
4kB RAM
ADuC7060/ADuC7061
RESET
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ON-CHIP
OSC (3%)
PLL
XTALI
XTALO
PRECISION
REFERENCE
IEXC0
IEXC1
DAC0
VREF+
VREF–
GND_SW
BUF
14-BIT
DAC
TEMP
SENSOR
4× TIMERS
WDT
W/U TIMER
PWM
GPIO PORT
UART PORT
SPI PORT
I
2
C PORT
VIC
(VECTORED
INTERRUPT
CONTROLLER)
Figure 1.
Rev. F | Page 5 of 107
07079-001
ADuC7060/
ADuC7061
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