SC74HC595
8-BIT SHIFT REGISTER (SERIAL INPUT, 3S PARALLEL OUTPUT WITH
LATCHES)
DESCRIPTION
SC74HC595 utilizes advanced CMOS technology, and has
8-bit shift register with serial input, serial/parallel output and 8-
bit tri-state output flip-latch. The pin configuration is in accord
with the 54LS/74LS series, and the operating speed is similar
to 54LS/74LS. This circuit has the protecting circuit for all the
inputs and outputs to avoid the damage caused by the static
discharge. And it has the ability of driving load and features
high noise immunity.
The register and flip-latch both have separate clock inputs
(SCK and RCK). The serial input data (IS) is stored into
register at the rising edge of SCK; the data of register is stored
into flip-latch at the rising edge of RCK. The low level of clear
port (
SCLR
) only reset the register, and is no effect to flip-
latch. When the control enable (
G
) is high level, the parallel-
out is level Z.
DIP-16-300-2.54 TSSOP-16-225-0.65
SSOP-16-300-0.65
SOP-16-300-1.27
SOP-16-225-1.27
ORDERING INFORMATION
Device
SC74HC595
2~6V
1µA
15 LS-TTL loads
f
max
=55MHz (V
CC
=5V)
80µA
SC74HC595A
SC74HC595B
SC74HC595C
SC74HC595D
Package
DIP-16-300-2.54
SOP-16-225-1.27
SOP-16-300-1.27
TSSOP-16-225-0.65
SSOP-16-300-0.65
FEATURES
* Wide operating voltage range
* Low input current
* High output driving ability
* High operating speed(Typical)
* Low supply current
APPLICATIONS
* LED screen
RECOMANDED OPERATING CONDITIONS
Characteristics
Power Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Symbol
V
CC
V
IN
V
OUT
T
opr
V
CC
=2.0V
Input Rise and Fall Time
T
r
, T
f
V
CC
=4.5V
V
CC
=6.0V
Ratings
2~6
0~V
CC
0~V
CC
-40~+85
0~1000
0~500
0~400
Unit
V
V
V
°C
ns
ns
ns
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http
:
www.silan.com.cn
REV:1.0
2006.04.19
Page 1 of 13
SC74HC595
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF INPUT T
r
=Tf=6ns T
amb
=25°C)
Characteristics
Symbol
Testing conditions
V
CC
(V)
2.0
Output Transition Time (Qn)
t
TLH
t
THL
4.5
6.0
2.0
Output Transition Time (QH’
)
t
TLH
t
THL
4.5
6.0
2.0
Propagation Delay Time(SCK-
QH’
)
t
PLH
t
PHL
4.5
6.0
2.0
Propagation Delay Time
(SCLR-QH’
)
t
PLH
t
PHL
4.5
6.0
2.0
4.5
Propagation Delay Time (RCK-
QN)
t
PLH
t
PHL
6.0
2.0
4.5
6.0
2.0
4.5
Tri-state Output Enable Time
t
PZL
t
PZH
6.0
2.0
4.5
6.0
2.0
Tri-state Output Disable Time
t
PLZ
t
PHZ
4.5
6.0
2.0
4.5
6.0
Maximum Clock
f
MAX
2.0
4.5
6.0
150
50
50
R
L
=1kΩ
150
R
L
=1kΩ
50
R
L
=1kΩ
150
50
50
50
50
50
CL(pF)
Min.
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
6.0
30
35
5.2
26
31
Typ.
25
7
6
30
8
7
45
15
13
60
18
15
60
20
17
75
25
22
45
15
13
60
20
17
30
15
14
17
50
59
14
40
45
Max.
60
12
10
75
15
13
125
25
21
175
35
30
150
30
26
190
38
32
135
27
23
175
35
30
150
30
26
--
--
--
--
--
--
(To be continued)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http
:
www.silan.com.cn
REV:1.0
2006.04.19
Page 4 of 13
SC74HC595
(Continued)
Characteristics
Symbol
Testing conditions
V
CC
(V)
2.0
CL(pF)
Min.
--
Typ.
17
6
6
20
6
6
25
5
4
35
8
6
40
10
7
--
--
--
15
3
3
5
184
Max.
75
15
13
75
15
13
50
10
9
75
15
13
100
20
17
0
0
0
50
10
9
10
Unit
Minimum Pulse Width
(SCK, RCK)
t
W(H)
4.5
6.0
2.0
50
--
--
--
ns
Minimum Pulse Width
(
SCLR
)
t
W(L)
4.5
6.0
2.0
50
--
--
--
ns
Minimum Set-up Time
(SI-SCK)
t
S
4.5
6.0
2.0
50
--
--
--
ns
Minimum Set-up Time
(SCK-RCK)
t
S
4.5
6.0
2.0
50
--
--
--
ns
Minimum Set-up Time
(
SCLR
-RCK)
t
S
4.5
6.0
2.0
50
--
--
--
ns
Minimum Hold Time
t
H
4.5
6.0
2.0
50
--
--
--
ns
Minimum Clear Time
t
REM
4.5
6.0
50
--
--
--
--
ns
Input Capacitance
Power Dissipation Capacitance
C
IN
C
PD
(*)
pF
pF
(*): CPD is defined as the internal equivalent capacitance of the IC. It is calculated from the operating current
without load; and the average operating current can be obtained by the equation: I
CC
(opr) =C
PD
*V
CC
*f
IN
+I
CC
.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http
:
www.silan.com.cn
REV:1.0
2006.04.19
Page 5 of 13
DSP and ARM Processors
京公网安备 11010802033920号
EEWORLD
