HR7P293

Parameters

• Kernel

- High-performance Harvard RISC CPU core

- 66 simplified instructions

- The system clock frequency is up to 16MHz

- 8-level program stack (PC hardware stack)

- The reset vector is located at 0000H, the default interrupt vector is located at 0004H, and interrupt priority and vector table are supported

- Support hardware divider

- Support interrupt processing, 17 interrupt sources

• Storage resources

- 8K Words FLASH program memory

- 496 Bytes SRAM data memory

- Program memory supports direct addressing

- Data memory supports direct addressing and indirect addressing

• I/O ports

- Supports 41 I/O ports

- PA port (PA0~PA4, PA6 and PA7)

- PB port (PB0~PB7)

- PC port (PC0~PC7)

- PD port (PD0~PD7)

- PE port (PE0~PE5)

- PF port (PF0~PF3)

- Support 4 external port interrupts (PINT0~PINT3)

- Supports 1 4-input external key interrupt KINT (input terminals are KIN0~KIN3)

• Peripherals

- One 8-bit timer T8N

- Timer mode (clock source is system clock divided by 4)

- Counter mode (clock source is T8NCKI input)

- Support configurable prescaler

- Support interrupt generation

- Three 8-bit PWM time base timers T8P1/T8P2/T8P3

- Timer mode (clock source is system clock divided by 4)

- Supports configurable prescaler and postscaler

- Support pulse width modulation extension function

- Support interrupt generation

- One 16-bit gated timer T16G

- Timer mode (clock source is system clock divided by 4)

- Counter mode (clock source is T16GCKI input or LP crystal oscillator)

- Support configurable prescaler

- Support external gate timing/counting

- Support comparator extension function

- Support for extended functions of the capturer

- Support pulse width modulation extension function

- Support interrupt generation

- Analog-to-digital converter (ADC)

- Support 10-digit conversion accuracy

- Support 10-channel analog input

- Support internal ADC RC clock source

- Support interrupt generation

- One high-speed asynchronous receiver and transmitter UART

- Support asynchronous full-duplex transmission and reception

- Support baud rate generator

- Support 8-bit/9-bit data format

- Agreement to receive/send from the lowest bit

- Support interrupt generation

- Support sending pulse width modulation mode

- One IIC bus master IICM

- Only supports single-master control mode, does not support multi-master arbitration mode and slave mode

- Support standard IIC bus protocol, maximum transmission rate 400Kbit/s

- Supports IIC communication signal completion interrupt flag, which must be cleared by software.

- 7-bit addressing mode is supported by software.

- The clock line (SCL) does not support wait request operation (slave pulls down the clock line).

- The data line (SDA) uses an open-drain design and must use an internal weak pull-up or an external pull-up resistor.

－ Liquid crystal display controller LCDC

- Support 8COM x 24SEG pixels

• special function

- Internal 16MHz oscillator

- Dividable frequency for main system clock source

- At 25°C, 3.0V~5V, the calibration accuracy is ±2%

- Supports two low power modes, IDLE0 mode and IDLE1 mode and wake-up operation

- Built-in power-on reset circuit

- Built-in low voltage detection and reset circuit

- Support watchdog timer

- Support prescaler

- Support internal watchdog RC clock source

- Support wake-up in IDLE0 mode or IDLE1 mode

- Support self-programming function

- Support In-Circuit Programming (ISP) interface

- Supports In-Circuit Debug (ICD) interface

- Support programming code protection

• Design and craftsmanship

- Low power consumption, high speed FLASH CMOS process

- 44 pins, LQFP package

• Working conditions

- Operating voltage range: 3.0V ~ 5.5V

- Operating temperature range: -40 ~ 85℃