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BC639-10

Description
Transistor
CategoryDiscrete semiconductor    The transistor   
File Size297KB,1 Pages
ManufacturerJCET
Websitehttp://www.cj-elec.com/

Jiangsu Changdian Technology Co., Ltd. focuses on semiconductor packaging and testing business, providing customers at home and abroad with a full range of solutions such as chip testing, packaging design, packaging testing, etc. The company was successfully listed on the Shanghai Main Board in 2003, becoming the first semiconductor packaging and testing listed company in China. It now has a national enterprise technology center and a postdoctoral research workstation. It is a national key high-tech enterprise, a supporting unit of the National Engineering Laboratory for High-density Integrated Circuits, and the chairman unit of the Integrated Circuit Packaging Technology Innovation Strategic Alliance.

Discrete devices: diodes (switching diodes, Schottky diodes (Schottky rectifiers), voltage regulator diodes, Pin diodes, TVS diodes, rectifier diodes, fast recovery diodes); transistors (Darlington tubes, digital transistors, MOSFETs); thyristors: silicon-controlled rectifiers, triacs; composite tubes: transistors + field-effect tubes, dual transistors, dual digital transistors, digital transistors + transistors, transistors + diodes, field-effect tubes + diodes, dual field-effect tubes. Voltage regulator circuit; energy-saving lamp charger switch tube

Lead frame: TO series (TO); SOD series (SOD); SOT series (TSOT, SOT); FBP series (WBFBP); QFN series (QFNWB, DFNWB, DFNFC, QFNFC); ​​QFP series (LQFP: PQFP: PLCC: TQFP); SIP series (SIP, HSIP, FSIP); SOP series (SOP, HSOP, SSOP, MSOP, HTSOP, TSSOP); DIP series (DIP, FDIP, SDIP); PDFN series; PQFN series; MIS series (MISFC, MISWB)

Nine core technologies: Through Silicon Via (TSV) packaging technology; SiP RF packaging technology; wafer-level 3D rewiring packaging process technology; copper bump interconnection technology; high-density FC-BGA packaging and testing technology (Flip Chip BGA); multi-turn array four-sided pinless packaging and testing technology; package body 3D stacking technology; 50μm or less ultra-thin chip 3D stacking packaging technology; MEMS multi-chip packaging technology; MIS packaging technology (pre-encapsulated interconnection system); BGA packaging technology, etc.

 

 

Download Datasheet Parametric View All

BC639-10 Overview

Transistor

BC639-10 Parametric

Parameter NameAttribute value
MakerJCET
package instruction,
Reach Compliance Codeunknown

BC639-10 Preview

Download Datasheet
JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO., LTD
TO-92
BC635/637/639
FEATURES
High current transistors
Plastic-Encapsulate Transistors
TO-92
TRANSISTOR (NPN)
1. EMITTER
2. COLLECTOR
3. BASE
MAXIMUM RATINGS (T
a
=25
unless otherwise noted)
Symbol
V
CBO
Collector-Emitter Voltage
Parameter
BC635
BC637
BC639
V
CEO
Collector-Emitter Voltage
BC635
BC637
BC639
V
EBO
I
C
P
C
T
J
T
stg
Emitter-Base Voltage
Value
45
60
100
45
60
80
5
1
0.625
150
-65-150
Unit
V
V
V
V
V
V
V
A
W
Typ
Max
Unit
V
V
V
0.1
0.1
μA
μA
Collector Current -Continuous
Collector Power Dissipation
Junction Temperature
Storage Temperature
ELECTRICAL CHARACTERISTICS (T
a
=25
unless otherwise specified)
Parameter
Symbol
V
(BR)CEO
I
CBO
I
EBO
h
FE(1)
h
FE(2)
DC current gain
h
FE(3)
Collector-emitter saturation voltage
Base-emitter voltage
Transition frequency
V
CE(sat)
V
BE
f
T
V
CB
= 30 V,I
E
=0
V
EB
=5V, I
B
=0
V
CE
=2 V, I
C
= 5mA
V
CE
=2V, I
C
=150mA
BC635
BC637-10/BC639-10
BC637-16/BC639-16
V
CE
=2V, I
C
= 500mA
I
C
=500mA, I
B
=50mA
V
CE
=2V, I
C
=500mA
V
CE
=5V, I
C
=10mA,f= 50 MH
Z
100
25
40
63
100
25
0.5
1
V
V
MHz
250
160
250
Test
conditions
BC635
BC637
BC639
Collector cut-off current
Emitter cut-off current
Min
45
60
80
I
C
=10mA, I
B
=0
Collector-emitter breakdown voltage
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