2SD313E datasheet, PDF - EEWORLD Datasheet

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2SD313E: DescriptionTransistor; CategoryDiscrete semiconductor The transistor; File Size137KB，1 Pages; ManufacturerJCET; Websitehttp://www.cj-elec.com/; Jiangsu Changdian Technology Co., Ltd. focuses on semiconductor packaging and testing business, providing customers at home and abroad with a full range of solutions such as chip testing, packaging design, packaging testing, etc. The company was successfully listed on the Shanghai Main Board in 2003, becoming the first semiconductor packaging and testing listed company in China. It now has a national enterprise technology center and a postdoctoral research workstation. It is a national key high-tech enterprise, a supporting unit of the National Engineering Laboratory for High-density Integrated Circuits, and the chairman unit of the Integrated Circuit Packaging Technology Innovation Strategic Alliance.

Discrete devices: diodes (switching diodes, Schottky diodes (Schottky rectifiers), voltage regulator diodes, Pin diodes, TVS diodes, rectifier diodes, fast recovery diodes); transistors (Darlington tubes, digital transistors, MOSFETs); thyristors: silicon-controlled rectifiers, triacs; composite tubes: transistors + field-effect tubes, dual transistors, dual digital transistors, digital transistors + transistors, transistors + diodes, field-effect tubes + diodes, dual field-effect tubes. Voltage regulator circuit; energy-saving lamp charger switch tube

Lead frame: TO series (TO); SOD series (SOD); SOT series (TSOT, SOT); FBP series (WBFBP); QFN series (QFNWB, DFNWB, DFNFC, QFNFC); QFP series (LQFP: PQFP: PLCC: TQFP); SIP series (SIP, HSIP, FSIP); SOP series (SOP, HSOP, SSOP, MSOP, HTSOP, TSSOP); DIP series (DIP, FDIP, SDIP); PDFN series; PQFN series; MIS series (MISFC, MISWB)

Nine core technologies: Through Silicon Via (TSV) packaging technology; SiP RF packaging technology; wafer-level 3D rewiring packaging process technology; copper bump interconnection technology; high-density FC-BGA packaging and testing technology (Flip Chip BGA); multi-turn array four-sided pinless packaging and testing technology; package body 3D stacking technology; 50μm or less ultra-thin chip 3D stacking packaging technology; MEMS multi-chip packaging technology; MIS packaging technology (pre-encapsulated interconnection system); BGA packaging technology, etc.

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2SD313E Overview

Transistor

2SD313E Parametric

Parameter Name	Attribute value
package instruction	,
Reach Compliance Code	unknow
Maximum collector current (IC)	3 A
Configuration	Single
Minimum DC current gain (hFE)	100
Maximum operating temperature	150 °C
Polarity/channel type	NPN
Maximum power dissipation(Abs)	1.75 W
surface mount	NO
Base Number Matches	1

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JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO., LTD

TO-220 Plastic-Encapsulate Transistors

2SD313

TRANSISTOR (NPN)

TO-220

1. BASE

2. COLLECTOR

3. EMITTER

FEATURES

Low Collector-Emitter Saturation Voltage

Vce(sat)=1V(MAX)@I

=2A,I

=0.2A

DC Current Gain h

=40~320@I

=1A

Complementray to PNP 2SB507

MAXIMUM RATINGS (T

=25℃ unless otherwise noted)

Symbol

CBO

CEO

EBO

stg

Parameter

Collector-Base Voltage

Collector-Emitter Voltage

Emitter-Base Voltage

Collector Current -Continuous

Collector Power Dissipation

Junction Temperature

Storage Temperature

Value

1.75

150

-55-150

Unit

℃

ELECTRICAL CHARACTERISTICS (T

=25℃

Parameter

Collector-base breakdown voltage

Collector-emitter breakdown voltage

Emitter-base breakdown voltage

Collector cut-off current

Emitter cut-off current

DC current gain

FE(2)

Collector-emitter saturation voltage

Base-emitter voltage

Transition frequency

Collector output capacitance

CE(sat)

Symbol

(BR)CBO

(BR)CEO

(BR)EBO

CBO

CEO

EBO

FE(1)

unless otherwise specified)

Test

=100μA, I

=1mA, I

=100μA, I

=60V, I

=4V, I

=2V, I

=1A

=2V, I

=0.1A

=2A, I

=200mA

=2V, I

=1A

=5V, I

=500mA

=10V, I

=0,f=1MHz

1.5

MHz

conditions

Min

100

320

Typ

Max

Unit

μA

CLASSIFICATION OF

Rank

Range

FE(1)

40-80

60-120

100-200

160-320

A,Mar,2011

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