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2SA1774R

Description
Transistor
CategoryDiscrete semiconductor    The transistor   
File Size87KB,2 Pages
ManufacturerJCET
Websitehttp://www.cj-elec.com/

Jiangsu Changdian Technology Co., Ltd. focuses on semiconductor packaging and testing business, providing customers at home and abroad with a full range of solutions such as chip testing, packaging design, packaging testing, etc. The company was successfully listed on the Shanghai Main Board in 2003, becoming the first semiconductor packaging and testing listed company in China. It now has a national enterprise technology center and a postdoctoral research workstation. It is a national key high-tech enterprise, a supporting unit of the National Engineering Laboratory for High-density Integrated Circuits, and the chairman unit of the Integrated Circuit Packaging Technology Innovation Strategic Alliance.

Discrete devices: diodes (switching diodes, Schottky diodes (Schottky rectifiers), voltage regulator diodes, Pin diodes, TVS diodes, rectifier diodes, fast recovery diodes); transistors (Darlington tubes, digital transistors, MOSFETs); thyristors: silicon-controlled rectifiers, triacs; composite tubes: transistors + field-effect tubes, dual transistors, dual digital transistors, digital transistors + transistors, transistors + diodes, field-effect tubes + diodes, dual field-effect tubes. Voltage regulator circuit; energy-saving lamp charger switch tube

Lead frame: TO series (TO); SOD series (SOD); SOT series (TSOT, SOT); FBP series (WBFBP); QFN series (QFNWB, DFNWB, DFNFC, QFNFC); ​​QFP series (LQFP: PQFP: PLCC: TQFP); SIP series (SIP, HSIP, FSIP); SOP series (SOP, HSOP, SSOP, MSOP, HTSOP, TSSOP); DIP series (DIP, FDIP, SDIP); PDFN series; PQFN series; MIS series (MISFC, MISWB)

Nine core technologies: Through Silicon Via (TSV) packaging technology; SiP RF packaging technology; wafer-level 3D rewiring packaging process technology; copper bump interconnection technology; high-density FC-BGA packaging and testing technology (Flip Chip BGA); multi-turn array four-sided pinless packaging and testing technology; package body 3D stacking technology; 50μm or less ultra-thin chip 3D stacking packaging technology; MEMS multi-chip packaging technology; MIS packaging technology (pre-encapsulated interconnection system); BGA packaging technology, etc.

 

 

Download Datasheet Parametric View All

2SA1774R Overview

Transistor

2SA1774R Parametric

Parameter NameAttribute value
package instruction,
Reach Compliance Codeunknow
Maximum collector current (IC)0.15 A
ConfigurationSingle
Minimum DC current gain (hFE)180
Maximum operating temperature150 °C
Polarity/channel typePNP
Maximum power dissipation(Abs)0.15 W
surface mountYES
Base Number Matches1

2SA1774R Preview

Download Datasheet
JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO., LTD
SOT-523 Plastic-Encapsulate Transistors
SOT-523
2SA1774
FEATURES
Power dissipation
P
CM
TRANSISTOR (PNP)
1.
BASE
2.
EMITTER
3.
COLLECTOR
: 0.15
W (Tamb=25℃)
Collector current
: -0.15
A
I
CM
Collector-base voltage
V
V
(BR)CBO
: -60
Operating and storage junction temperature range
T
J
, T
stg
: -55℃ to +150℃
ELECTRICAL CHARACTERISTICS (Tamb=25℃
Parameter
Collector-base breakdown voltage
Collector-emitter breakdown voltage
Emitter-base breakdown voltage
Collector cut-off current
Emitter cut-off current
DC current gain
Collector-emitter saturation voltage
Transition frequency
Collector output capacitance
Symbol
V
(BR)CBO
V
(BR)CEO
V
(BR)EBO
I
CBO
I
EBO
h
FE(1)
V
CE(sat)
unless otherwise specified)
Test
conditions
MIN
TYP
MAX
UNIT
V
V
V
Ic=-
50
µA,
I
E
=0
Ic=-
1
mA, I
B
=0
I
E
=-
50
µA,
I
C
=0
V
CB
=-
60
V, I
E
=0
V
EB
=-
6
V, I
C
=0
V
CE
=-
6
V, I
C
=-
1
mA
I
C
=-
50
mA, I
B
=-
5
mA
V
CE
=-
12
V, I
C
=-
2
mA, f=30MHz
V
CB
=-
12
V, I
E
=0, f=
1
MHz
-60
-50
-7
-0.1
-0.1
120
560
-0.5
140
5
µA
µA
V
MHz
pF
f
T
C
ob
CLASSIFICATION OF h
FE(1)
Rank
Range
Marking
Q
120-270
FQ
R
180-390
FR
S
270-560
FS
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