DATA SHEET
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Advanced Synchronous
Rectifier Controller for LLC
Resonant Converter
NCP4318
NCP4318 is an advanced synchronous rectification (SR) controller
for LLC resonant converter with minimum external components. It
has two gate drivers for driving the SR MOSFETs rectifying the
outputs of the secondary transformer windings. The two gate drivers
have their own drain and source sensing pins and operate
independently of each other. The advanced adaptive dead time control
compensates the voltage across parasitic inductance to minimize the
body diode conduction and maximize the system efficiency. The
advanced turn−off control algorithm allows stable SR operation over
entire load range. NCP4318 has two versions of pin assignment –
NCP4318A, NCP4318B, and two types of package – SOIC−8 and
SOIC−8 EP.
Features
8
1
SOIC−8 EP
CASE 751AC
8
1
SOIC−8, 150 mils
CASE 751BD
MARKING DIAGRAM
8
NCP4318
UVWX
AWLYYWW
1
U
= Pin Layout, A and B
V
= Frequency, H: High, L: Low
WX = Additional IPT Option
A
= Assembly Location
WL = Wafer Lot Traceability
YYWW = Date Code
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Mixed Mode SR Turn−off Control
Anti Shoot−through Control for Reliable SR Operation
200 V−rated Drain Sensing and Dedicated Source Sensing Pins
Advanced Adaptive Dead Time Control
SR Current Inversion Detection
Adaptive Minimum Turn−on Time for Noise Immunity
SR Conduction Time Increase Rate Limitation
Multi−level Turn−off Threshold Voltage
Adaptive Gate Voltage (10 V, 6 V)
Low Operating Current (100
mA)
in Green Mode
Soft Start with 0 V / 6 V Gate Output Voltage
Short Turn−on and Turn−off Delay Time (30 ns / 30 ns)
High Gate Sourcing and Sinking Current (1.5 A / 4.5 A)
Wide Operating Supply Voltage Range from 6.5 V to 35 V
Wide Operating Frequency Range (22 kHz to 500 kHz)
SOIC−8 and SOIC−8 EP Packages
These Devices are Pb−Free and are RoHS Compliant
High Power Density Adapters
Large Screen LED−TV and OLED−TV Power Supplies
High Efficiency Desktop and Server Power Supplies
Networking and Telecom Power Supplies
High Power LED Lighting
PIN CONNECTIONS
NCP4318AXX
GATE1
GATE2
GND
VDD
VS1
VD2
VD1
VS2
NCP4318BXX
GATE1
GATE2
GND
VDD
VD1
VD2
VS1
VS2
(Top View)
Applications
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 3 of this data sheet.
©
Semiconductor Components Industries, LLC, 2020
September, 2021
−
Rev. 4
1
Publication Order Number:
NCP4318/D
NCP4318
M2
R
offset2
Bridge
Diode
Optional
V
AC
EMI
Filter
PFC
Stage
C
in
Q
1
C
r
L
r
NCP4318A
V
O
G2
VD1 VS2
VS1 VD2
GND VDD
Q
2
L
p
R
offset1
LLC
Controller
M1
G1
C
O
R
O
Optional
Shunt
Regulator
Figure 1. Typical Application Schematic of NCP4318
VD1_HIGH
SR
Conduction
V
TH−HGH
I
OFFSET1
DLY_EN1
VD1
V
TH−ON
Adaptive
turn−
on
delay
RUN
D
SET
Turn−
on
CLR
VD2_HIGH
SRCOND1
SRCOND2
SR
Conduction
V
TH−HGH
I
OFFSET2
RUN
Q
Q
SET
DLY_EN2
VD2
V
TH−ON
D
Q
Q
CLR
Adaptive
turn−on
Turn−on
delay
VS1
V
TH−OFF1
Turn−
off
Adaptive
Tmin−on
Adaptive
V
GATE
V
D1−HGH
GATE
CLAMP
SRCINV1
Turn−
off
SRCINV2
Adaptive
Tmin−on
V
TH−OFF2
VS2
Adaptive
dead time
control
I
OFFSET1
V
TH−OFF1
I
OFFSET2
V
TH−OFF2
Adaptive
dead time
control
Adaptive
V
GATE
V
D2−HGH
GATE
CLAMP
GATE2
GATE1
VG1
VD1
GREEN
VD2
VG2
SR Current Inversion detect
SRCINV1
V
DD−GATE−ON
/ V
DD−GATE−OFF
GREEN
DLY_EN1
DLY_EN2
SRCINV2
SRCOND1,2
VD1_HGH
Protections
V
TH−OFF1
HFS
OTP1
V
GATE
Control
Adaptive
V
GATE
SRCOND1
SRCOND2
SOFT
START
RUN
GREEN MODE
GREEN
SS_7V
VDD
GND
Figure 2. Internal Block Diagram of NCP4318
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2
NCP4318
PIN DESCRIPTION
Pin Number
NCP4318A
1
2
3
4
NCP4318B
1
2
4
3
Name
GATE1
GND
VS1
VD1
Gate drive output for SR MOSFET1
Ground
Synchronous rectifier source sense input for SR1
Synchronous rectifier drain sense input. I
OFFSET1
current source flows out of the VD1
pin such that an external series resistor can be used to adjust the synchronous rectifi-
er turn−off threshold. The I
OFFSET1
current source is turned off when V
DD
is under−
voltage or when switching is disabled in green mode
Synchronous rectifier source sense input for SR2
Synchronous rectifier drain sense input. I
OFFSET2
current source flows out of the VD2
pin such that an external series resistor can be used to adjust the synchronous rectifi-
er turn−off threshold. The I
OFFSET2
current source is turned off when V
DD
is under−
voltage or when switching is disabled in green mode
Supply Voltage
Gate drive output for SR MOSFET2
Description
5
6
5
6
VS2
VD2
7
8
7
8
VDD
GATE2
ORDERING INFORMATION
Ordering Code
NCP4318AHDDR2G
NCP4318AHJDR2G
NCP4318ALCDR2G
NCP4318ALKDR2G
NCP4318ALSDR2G
NCP4318BLCDR2G
NCP4318ALFPDR2G
‡
Device Marking
NCP4318AHD
NCP4318AHJ
NCP4318ALC
NCP4318ALK
NCP4318ALS
NCP4318BLC
NCP4318ALFP
SOIC−8 EP
(Pb−Free)
Package
SOIC−8
(Pb−Free)
Shipping
†
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
‡In development. Available upon request.
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3
NCP4318
MAXIMUM RATINGS
Symbol
V
DD
V
D1,
V
D2
V
GATE1,
V
GATE2
V
S1,
V
S2
V
S1−DYN,
V
S2−DYN
P
D
Power Supply Input Pin Voltage
Drain Sense Input Pin Voltage
Gate Drive Output Pin Voltage
Source Sense Input Pin Voltage
Source Sense Input Pin Dynamic Voltage (Pulse Width = 200 ns)
Power Dissipation (T
A
= 25°C)
SOIC−8
SOIC−8 EP
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10 Seconds)
Electrostatic Discharge Capability
Human Body Model,
ANSI / ESDA / JEDEC JS−001−2012
(except VD1, VD2 pin)
Human Body Model,
VD1−GND, VD2−GND pin to pin with 330−pF (Note 2)
capacitance on VD1 and VD2 pin
Charged Device Model, JESD22−C101
Rating
Value
−0.3
to 37
−4
to 200
−0.3
to 17
−0.3
to 5.5
−4
to 5.5
Unit
V
V
V
V
V
W
0.625
TBD
−40
to 150
−60
to 150
260
3
T
J
T
STG
T
L
ESD
°C
°C
°C
kV
2
1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. All voltage values are with respect to the GND pin.
2. The capacitance can be replaced by C
OSS
of MOSFET.
THERMAL CHARACTERISTICS
Symbol
R
qJA
Thermal Resistance, Junction−to−Ambient.
SOIC−8 (Note 3)
SOIC−8 EP (Note 4)
Thermal Characterization Parameter between Junction and the Center of the Top of the Package.
SOIC−8 (Note 3)
SOIC−8 EP (Note 4)
Rating
Value
165
40
22
4
Unit
°C/W
R
yJT
°C/W
3. JEDEC standard: JESD51−2 (still air natural convection) and JESD51−3 (1s0p).
4. JEDEC standard: JESD51−2 (still air natural convection) and JESD51−7 (2s2p) with an additional 1−oz 1−in
2
copper spreader.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
DD
V
D1
, V
D2
V
S1
, V
S2
T
J
Rating
VDD Pin Supply Voltage to GND (Note 5)
Drain Sense Input Pin Voltage
Source Sense Input Pin Voltage
Operating Junction Temperature
Min
0
−0.7
−0.3
−40
Max
35
180
5
+125
Unit
V
V
V
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. Allowable operating supply voltage V
DD
can be limited by the power dissipation of NCP4318 related to switching frequency, load capacitance
and ambient temperature.
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4
NCP4318
ELECTRICAL CHARACTERISTICS
(V
DD
= 12 V and T
J
=
−40°C
to 125°C unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
SUPPLY VOLTAGE AND CURRENT SECTION
V
DD−ON
V
DD−OFF
V
DD−GATE−ON
Turn−on Threshold
Turn−off Threshold
SR Gate Enable Threshold Voltage
V
DD
rising with 4.3 V / 1 ms
V
DD
< V
DD−OFF
V
DD
> V
DD−GATE−ON
V
DD
< V
DD−GATE−OFF
f
SW
= 100 kHz, C
GATE
= 1 nF
f
SW
= 100 kHz, C
GATE
= 0 nF
V
DD
= V
DD−ON
−
0.1 V
V
DD
= 12 V (no V
D1/2
switching)
GREEN1 enable at T
J
= 25°C
V
D1/2
falling lower than V
TH−ON
& V
D1/2
rising higher than V
TH−HGH
& No GATE
output at f
SW
= 200 kHz, C
GATE
= 0 nF
−
3.6
−
5.0
−
−
−
−
−
4.0
3.8
6.5
6.0
8
−
−
100
255
4.3
−
7.1
−
10
6
100
210
−
V
V
V
V
mA
mA
mA
mA
Cycle
V
DD−GATE−OFF
SR Gate Disable Threshold Voltage
(Note 6)
I
DD−OP1
I
DD−OP0
I
DD−START
I
DD−GREEN
h
SS
−
SKIP
Operating Current
Operating Current
Start−up Current
Operating Current in Green Mode
Number of V
D1/2
Alternative
Switching for Soft Start Skipping
DRAIN VOLTAGE SENSING SECTION
V
OSI
I
DRAIN−LKG
V
TH−ON
t
OFF−MIN
Comparator Input Offset Voltage
(Note 6)
Drain Pin Leakage Current
Turn−on Threshold (Note 6)
Minimum Off−time
V
D1/2
= 200 V
R
OFFSET
= 0
W
(includes comparator
input offset voltage)
From V
D1/2
higher than V
TH−HGH
in ALC, ALK, BLC, ALFP
in ALS
in AHD, AHJ
Turn−on comparator delay
From V
D1/2
=
−0.2
to V
GATE
= 1 V, when
DLY_EN = 0
Turn−on comparator delay
From V
D1/2
=
−0.2
to V
GATE
= 1 V, when
DLY_EN = 1.
in AHD, AHJ, ALC, ALK, ALS, BLC, ALFP
Turn−off comparator delay
From V
D1/2
= 0.6 to V
GATE
= 5.7 V
R
OFFSET
= 0
W
(includes comparator
input offset voltage)
in ALC, ALK, ALS, BLC, ALFP
in AHD, AHJ
R
OFFSET
= 0
W
in AHD, AHJ, ALC, BLC, ALFP
in ALK, ALS
R
OFFSET
= 0
W,
in ALC, BLC, ALFP
in ALK, ALS
in AHD, AHJ
R
OFFSET
= 0
W,
in ALC, BLC, ALFP
in ALK, ALS
in AHJ
LLD = 0.
If LLD
≥
1, 2
nd
step V
TH−OFF
= V
TH−OFF
LLD = 0, t
VG1
(n−1) = 8
ms,
and K
2ND−TOFF
*
t
VG1
(n−1) > t
MIN−ON.
If K
2ND−TOFF
* t
VG1
(n−1) < t
MIN−ON
,
t
VG1−70
= t
MIN−ON
−1
−
−
−100
0
1
1
−
mV
mA
mV
ns
1400
450
750
−
2000
800
1150
30
2800
1150
1550
80
t
ON−DLY
Turn−on Propagation Delay
ns
t
ON−DLY2
Turn−on De−bounce Time when
Additional Turn−on Delay is Enabled
(Note 6)
Turn−off Propagation Delay
Minimum Turn−off Threshold Voltage
(Note 6)
ns
−
−
240
30
−
80
ns
mV
−
−
−
−
−
−
−
−
−
−
−
−
−6
−14
4
8
118
242
110
2
10
−10
60
70
−
−
−
−
−
−
−
−
−
−
−
−
mV
t
OFF−DLY
V
TH−OFF−MIN
V
TH−OFF−STEP
Step Size of Adaptive Turn−off
Threshold Voltage (Note 6)
Maximum Turn−off Threshold
Voltage (Note 6)
V
TH−OFF−MAX
mV
V
TH−OFF−RST
Reset Value of Turn−off Threshold
Voltage (Note 6)
mV
K
2ND−VOFF
K
2ND−TOFF
Ratio of Second−step V
TH−OFF
to
V
TH−OFF
(Note 6)
Effective On−time Duration Ratio to
On−time of Last Switching Cycle for
the Second Step V
TH−OFF
(Note 6)
%
%
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