Automatic tuning circuit designed with notch filter

The circuit of this design is shown in the attached figure. It uses IC1 (74HC4046PLI. Phase-locked loop) integrated circuit chip, operating frequency 1MHz. To improve the noise resistance of the system. IC2. An RDD104 integrated circuit chip produced by LSI Computer Systems, which provides a 1000 to 1 divider in an 8-pin package. IC3. Mixed signal integrated MSHN51000 to 1 clock corner switched capacitor high pass, notch filter. It uses a popular 8-pin package.

Feed the output (vcoo) of IC1's vco (voltage controlled oscillator) into the clock input of IC2. IC2 can complete the distribution of 10, 100, 1000 and 100100 ratios by using DIV1 and DIV2, and then connect the output of RDD104 to the COIN of IC1. By using the EX/OR phase comparator of IC1, the noise resistance can be improved. Add the filter input signal to the input terminals of both IC1 (filter) and IC3 (filter). The CLK-OUT pin of IC2 drives the clock of IC3.

The MSHN5, IC3, has a selectable high-pass filter and a selectable notch filter. When you tie the FSEL pin high, it selects the notch. Tie TYPE to AGND to select the narrow notch filter. This step ensures that only one tone is removed from the input signal with loss of information. IC3's 1000-to-1 clock corner ratio reduces the chance that distorted signals will affect the output. For voice applications, for example, no signals of 500kHz or higher will likely fall into the passband. A sample device is clocked at 789.13kHz, 1000 times the input signal using an input frequency of 789.13MHz. The PLL tracks the input, moving the notch filter to 1.24kHz.