SIPMOS transistor control circuit diagram using photoelectric isolation

The input end is connected to ground through resistor R2, so that its output end is still open when the power supply voltage drops to 4V, that is, the two push-pull output transistors remain in the off state. This allows the photocoupler output side to remain low when the power supply voltage rises to about 3V, so that the following six inverters 4049 can control the SIPMOS transistor. During the working phase, the output terminal of the optocoupler is open, so that the output terminal of the six-inverter is high level and the output terminal is low level.