5G millimeter wave radio frequency technology

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5G millimeter wave radio frequency technology [Copy link]

Hybrid beamforming, such as shown in the figure, will be the preferred architecture for 5G systems operating at microwave and millimeter wave frequencies. This architecture uses a combination of digital (MIMO) and analog beamforming to overcome high path loss and improve spectral efficiency. As shown in the figure, a combination of m data streams are split onto n RF paths to form a beam in free space, so the total number of antenna elements is the product m × n. The digital streams can be combined in a variety of ways, either using high-level MIMO to direct all the energy to a single user or using multi-user MIMO to support multiple users.

A simple example of a massive antenna array is used to explore the optimal technology choice for millimeter wave radios. Now looking deeper into the block diagram of the radio portion of a millimeter wave system, we see a classic superheterodyne structure that converts microwave signals to digital signals, which are then connected to multiple RF signal processing paths, where microwave phase shifters and attenuators are used to achieve beamforming. Traditionally, millimeter wave systems are built using discrete components, resulting in large size and high cost. The components in such systems use technologies such as CMOS, SiGe BiCMOS and GaAs to achieve optimal performance for each component. For example, data converters are now developed using CMOS processes, allowing sampling rates to reach the GHz range. Up and down conversion and beamforming functions can be effectively implemented in SiGe BiCMOS. Depending on the system specifications, GaAs-based power amplifiers and low-noise amplifiers may be required, but if SiGe BiCMOS can meet the requirements, it will enable a higher level of integration. For 5G millimeter wave systems, the industry hopes to install microwave components on the back of the antenna substrate, which requires that the integration of microwave chips must be greatly improved. For example, the half-wave element spacing for an antenna with a center frequency of 28 GHz is approximately 5 mm. At higher frequencies, this spacing decreases, and chip or package size becomes an important consideration. Ideally, the entire block diagram for a single beam should be integrated into a single IC; in practical situations, at least the up and down converters and the RF front end should be integrated into a single RFIC. The level of integration and process selection are driven to some extent by the application, as we will see in the example analysis below. Example Analysis: Antenna Center Frequency at 28 GHz, EIRP at 60 dBm This analysis considers a typical base station antenna system with an EIRP requirement of 60 dBm. The following assumptions are used: Antenna Array Gain = 6 dBi (Boresight) Waveform PAPR = 10 dB (OFDM with QAM) PA PAE at P1dB = 30% Tx/Rx Switching Losses = 2 dB Tx/Rx Duty Cycle = 70%/30% Data Streams = 8 Power consumption of each circuit block is based on prior art. The model is built based on 8 data streams connected to different numbers of RF chains. The number of antennas in the model is scaled in multiples of 8 up to a maximum of 512 elements. The following figure shows how the PA linearity changes as the antenna gain increases. Note: The output power of the amplifier is 2 dB higher than the power delivered to the antenna due to switching losses. As you add elements to the antenna, the directional gain increases linearly with the logarithmic value of the x-axis, so the power requirements of each amplifier decrease. For illustration purposes, we have overlaid a graph of the technologies on the curves to indicate which technology is best for different ranges of antenna element counts. Note: There is overlap between the different technologies because each technology has a range of values that it works well for. In addition, there is a range of performance that can be achieved with a specific technology based on process and circuit design practices. With very few elements, each chain requires a high power PA (GaN and GaAs), but as the number of elements exceeds 200, P1dB drops below 20dBm, which is within the range that silicon processes can meet. When the number of elements exceeds 500, the PA performance is within the range that can be achieved with current CMOS technology. Now consider the power consumption of the antenna Tx system as the number of elements increases. As expected, power consumption is inversely proportional to antenna gain, but there is a limit. Beyond a few hundred elements, the power consumption of the PA no longer dominates, resulting in diminishing returns. The power consumption of the entire system is as expected, with the receiver power consumption increasing linearly as the number of RF chains increases. If we overlay the decreasing Tx power consumption curve on the increasing Rx power consumption curve, we can observe a minimum power consumption area. The minimum occurs at about 128 elements, and the best PA technology to achieve 60dBm EIRP with 128 elements is GaAs. While using a GaAs PA can achieve the lowest antenna power consumption and 60dBm EIRP, this may not meet all the requirements of the system design. As mentioned earlier, many cases require the RFIC to be placed within the λ/2 spacing of the antenna elements. Using a GaAs transmit/receive module can provide the required performance, but does not meet the size constraints. To utilize GaAs transmit/receive modules, alternative packaging and routing schemes are required. The preferred option may be to increase the number of antenna elements to use SiGe BiCMOS power amplifiers integrated into RFICs. By doubling the number of elements to approximately 56, the SiGe amplifier can meet the output power requirements. The increase in power consumption is small, and the SiGe BiCMOS RFIC can be placed within the λ/2 spacing of the antenna elements (28 GHz). Extending this approach to CMOS, it is found that CMOS can also achieve an overall 60dBm EIRP, but the number of elements is doubled from the technology diagram. Therefore, this approach will result in increased size and power consumption, and considering current technology limitations, the CMOS approach is not a viable option. Analysis shows that the best solution for achieving a 60dBm EIRP antenna today is to integrate SiGe BiCMOS technology into RFICs, considering both power consumption and integration size. However, if lower power antennas are considered for CPE, then CMOS is certainly a viable option. This analysis is based on currently available technology, but significant advances are being made in mmWave silicon processes and design techniques. We anticipate future silicon processes will have better energy efficiency and higher output power capabilities, which will enable smaller form factors and further optimization of antenna size. As the arrival of 5G approaches, designers will continue to face challenges. When determining the best technology solution for mmWave radio applications, it is beneficial to consider all aspects of the signal chain and the various advantages of different IC processes.