Design of Multi-channel ADC System Based on DSP and CPLD Technology[Copy link]
Author: Lin Chengbao and Liu Yanming, School of Communication Engineering, Xidian University With the application and development of modern electronic technology, the content of digital signal processing is becoming increasingly complex, and ADC is an inevitable process to achieve the conversion from analog to digital. In view of this situation, a design method of a multi-channel ADC system is proposed using digital signal processors and programmable logic devices, which realizes the sampling, transmission and processing of dynamic multi-channel analog input signals, simplifies the circuit design, and programmable logic devices make the system's versatility and portability well expanded. The system block diagram is shown in Figure 1. System
hardware design The ADC device used in this design is the low-power 16-bit analog-to-digital converter (ADC) MAX1162 produced by MAXIM. MAX1162 adopts a successive approximation ADC structure, with automatic shutdown, 1.1μs fast wake-up and high-speed interface compatible with SPI/QSPI/MICROWIRE, uses a +5V single analog power supply, and has an independent digital power supply pin, allowing the chip to directly interface with +2.7~+5.25V digital logic. The REF pin is connected to an external reference voltage, which is used to set the analog input voltage range. A 4.7μF electrolytic capacitor is connected to the analog ground. The AVDD pin is the +5V power supply input, and a 0.1μF capacitor is connected to the analog ground. AGND is the analog ground. CS is the chip select input, which is valid at low. When it is high, the system is in power-off mode. When it changes from high to low, the system is activated to the normal operating mode and a conversion is initialized. This system is selected as the enable signal of AD. SCLK is the serial clock input, which drives the analog-to-digital conversion process. DOUT is the serial data output, and the data state changes on the falling edge of SCLK. DGND is the digital ground. DVDD is the digital voltage supply, and a 0.1μF capacitor is connected to the digital ground. AIN is the analog signal input.
The central control unit of the ADC system uses the floating-point digital signal processor TMS320VC33-150 from TI (Texas Instruments). The address bus of TMS320VC33 is 24 bits, the program addressing range can reach 16M, the data bus is 32 bits, and it has 34K×32bit SRAM inside, which can be mapped in the program or data space as needed. It has a serial port that can transmit 8, 16, 24, 32 bits of data, and its transmission mode can be set to burst mode or continuous mode. Two 32-bit general-purpose timers can be used to communicate with the chip internally or externally at specified time intervals.
Considering that this system is mainly used in ADC, the data bus and address bus of TMS320VC33 are directly used without adding any additional circuits, so that the sampling speed and conversion accuracy of ADC are well guaranteed. At the same time, the INT2 and XF0 pins are used as the interrupt signal for DSP to receive data and the enable signal for ADC. INT2 is an external interrupt pin, which is triggered by external data input; XF0 is an external flag output pin, which is controlled by software and can be used to send signals to external devices. The state of this pin is determined by the I/O flag register. IOF=0X22, that is, XF0 is set as a general-purpose output pin, and the pin outputs 0; if IOF=0X26, XF0 is set as a general-purpose output pin, and the pin outputs 1. This system uses software instructions to set XF0 high or low to control the start and stop of ADC conversion.
EMP7512AE is based on EEPROM technology and adopts multi-voltage I/O interface technology. The system core supply voltage is 3.3V, and the I/0 pins are compatible with 2.5V, 3.3V, and 5.0V logic levels. EPM7512AE has 10,000 available gates, 512 macro cells, 32 logic array blocks, and 212 user-available I/0 pins. The main functions of CPLD in the system are: providing clock signals for ADC conversion, controlling the enable and reset of ADC conversion, and because the ADC chip used is serial output, CPLD also realizes the conversion of serial data input into parallel data output, and then directly connects to the data bus of TMS320VC33. At the same time, CPLD generates a pulse signal. After the ADC conversion is completed, the data is temporarily stored in CPLD. The pulse requests an interrupt to the CPU to prompt that there is data to be received. In addition, a key role of CPLD is to realize the dynamic selection of the number of channels. The current system has a maximum number of channels of 8. The specific hardware connection diagram of CPLD, DSP and AD chip is shown in Figure 2.
System Software Design In the software design, the CPLD program is used to dynamically control the ADC conversion, select the analog signal input terminal, enable the ADC, and complete the data sampling and transmission of the MAX1162 according to the conversion timing diagram shown in Figure 3. The main program part of the VHDL language is given below.
BEGIN ADCS <= SYNTHESIZED_WIRE_12; ADA <= SYNTHESIZED_WIRE_2; GDFX_TEMP_SIGNAL_1 <= (L & L & H & H & H & L); GDFX_TEMP_SIGNAL_0 <= (H & L & H & H & L); U1 : lpm_bustri_0----three-state bus buffer, allowing the sampled data to be output to the DSP data bus PORT MAP(enabledt => DRD, data => ADO, tridata => D); U2 : lpm_counter_1----counter, change the data bus width to 3 bits PORT MAP(sload => SYNTHESIZED_WIRE_0, clock => SYNTHESIZED_WIRE_1, aload => XFA0, data => CMD(2 downto 0), q => SYNTHESIZED_WIRE_2); U3 : lpm_dff_1---D flip-flop, data bus width is 8 bits, receiving data from DSP PORT MAP(clock => CMDCK, data => D(7 downto 0), q => CMD); U4 : lpm_compare_1---comparator, compares the values of CMD(5..3) and CMD(2..0), that is, polling sampling channel PORT MAP(dataa => CMD(5 downto 3), datab => SYNTHESIZED_WIRE_2, aeb => SYNTHESIZED_WIRE_0); SYNTHESIZED_WIRE_1 <= NOT(AQ(4)); NRW<= NOT RW; CMDCK<= NOT( NOT PAGE3 AND(NOT RW)AND A6 AND A5 AND A4 AND (NOT A3)); ----Channel control address coding DRD <= NOT PAGE3 AND RW AND A6 AND A5 AND A4 AND A3;----Sampling address coding CLKA <= Notice NTHESIZED_WIRE_5 , q = > ADO); SYNTHESIZED_WIRE_12 < = SQ ( 12 ) OR 0 OR XFA0; SYNTHESIZED_WIRE_3 < = _WIRE_6 AND SYNTHESIZED_WIRE_7 AND SYNTHESIZED_WIRE_8; SYNTHESIZED_WIRE_7 <= NOT(HFP(2)); SYNTHESIZED_WIRE_6 <= NOT(HFP(3)); INTA2 <= XFA0 OR SYNTHESIZED_WIRE_9; U6:lpm_shiftreg_1----Serial data input converted to parallel data output PORT MAP(shiftin => ADOUT, clock => HFP(5), q => SYNTHESIZED_WIRE_5);
U7 : lpm_counter_3---产生时钟信号 PORT MAP(sload => SYNTHESIZED_WIRE_10, clock => H1CK, data => GDFX_TEMP_SIGNAL_1, q => HFP); SYNTHESIZED_WIRE_8 <= NOT(HFP(1)); ADSCK <= NOT(HFP(5)); SYNTHESIZED_WIRE_9 <= NOT(SYNTHESIZED_WIRE_12); H <= '1'; L <= '0'; END;
提升卡
变色卡
千斤顶
京公网安备 11010802033920号
