Urgent help: LMK03806B sometimes outputs normally, but sometimes fails to output normally?

857795020

Urgent help: LMK03806B sometimes outputs normally, but sometimes fails to output normally? [Copy link]

Emergency help: LMK03806B can output normally sometimes, but not normally? LMK03806 chip is configured by Xilinx K7 FPGA, and the circuit reference manual is used. However, the input part does not have a capacitor or resistor, but directly connects a 0.1uF capacitor to the single-ended input Oscin. The amplitude of the 62MHz signal input after the 0.1uf capacitor at the input end is about 400mVpp, which meets the manual's 0.2Vpp~2.4Vpp input requirements. The output is 5 channels of 765.472MHz. One channel is configured as Lvcmos, and the other four channels are configured as lvds. At present, the test shows that sometimes the 65.472MHz output can be output normally, and sometimes there is nothing output, and then there is a 62MHz signal on one of the default output channels. It feels like the chip is in the default state? Help, has anyone encountered this situation? Some specific questions, please ask the experts! 1 In the 2018 version of the manual, page P22, there is a prompt as shown below: It is required to program R3 after power up. How do you understand this sentence? What is the programming sequence? I don't understand. Is it sequence A: R0 (only the reset bit is set to 1) -> R0 (normal configuration) -> R1 ->R2->R3->R4 ......... Or sequence B: R0 (only the reset bit is set to 1) -> R3 -> R0 (normal configuration) -> R1-> R2->R3->R4......... Or sequence C: R0 (only the reset bit is set to 1) -> R3 -> R0 (normal configuration) -> R1 -> R2 ->R4 ......... 2 Questions about SYNC. Page P34 in the manual. What is the function or meaning of this sync? I didn't understand it very well in the manual. A pin of the FPGA on my hardware is connected to this sync pin. Now in the configuration code, there is an operation of pulling the sync from high to low. How do you generally use this sync signal? How should the corresponding register be configured? As shown below, should it be configured as 1 or 0? 3 Questions about the loop filter. Page P36 of the manual says that a 3rd or 4th order loop filter can be completed by configuring the internal resistors and capacitors, without the need for external components. I would like to ask if the external filter on the cpout pin in the circuit can be connected to nothing? It is completely empty. It seems that the resistors and capacitors in the manual are only enough to make a 2nd order filter, not enough to make a 3rd or 4th order? My question is, if it sometimes locks and sometimes cannot lock, is it possible that there is a problem with the resistors and capacitors I selected for the external loop filter? So can I remove all the external resistors and capacitors and only use the internal resistors and capacitors to complete the loop filtering function? In this way, the signal can be locked quickly? Thank you, everyone. I hope you can help me if you have used it. Your guidance will illuminate our way forward. Thank you

alan000345

The first question is, It is required to program R3 after power up, which means R3 needs to be arranged after power on. The sequence c should be correct. The second question is, if it is configured to 1, it can achieve synchronous clock. If it is not used for phase-locked loop to achieve synchronous clock, it does not need to be set to 1. The third question, you can try it.

857795020

Thank you. I still don't understand it very well. Please write down the result after I have figured it out.