Complete real-time multi-channel signal acquisition, analysis and transmission. Because the analysis algorithm is more complicated, it is required to implement two AD7656 chips on the board for simultaneous timing sampling (but do not generate interrupts like in the routine), and only generate an interrupt after the data conversion is completed. According to this requirement, when programming, what are the requirements and restrictions on the timing of the *AD_CONVST, *ADREG, *AD_CHIPSEL0, *AD_CHIPSEL1 and other signals defined in the AD header file and the ADCCS0, ADCCS1, and ADCCSProFlag fields in the struct FLAG_BITS? Please advise. Specifically, the sampling is still channel by channel (see the AD7656 data sheet). Usually, after sampling one chip, another chip is sampled through chip selection. ADCCS1 and ADCCS0 in FLAG_BITS are used to specify which chip select to use, which is a variable. There is a gating control when sampling, which has no other use and has nothing to do with the hardware chip select. *AD_CONVST, *AD_CHIPSEL0, *AD_CHIPSEL1 The first signal mentioned is the actual chip select control. That is, the CS for each of the two AD chips. For the control timing, see the AD7656 data sheet.