[Repost] Popular Science of Components: How IC Chips Are Packaged

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[Repost] Popular Science of Components: How IC Chips Are Packaged [Copy link]

Getting an IC chip requires a long process from design to manufacturing. However, a chip is quite small and thin. If it is not protected from the outside, it will be easily scratched and damaged. In addition, because the chip is small in size, it will not be easy to place it on the circuit board manually without a larger shell. At this time, packaging technology comes in handy. Therefore, this article will describe and introduce packaging.

There are currently two common packaging methods. One is the black DIP package that looks like a centipede, which is common in electric toys, and the other is the BGA package that is common when buying boxed CPUs. As for other packaging methods, there are PGA (Pin Grid Array in Grid Array) used in early CPUs or QFP (Plastic Quad Flat Package), a modified version of DIP. Because there are so many packaging methods, the following will introduce DIP and BGA packaging.

Traditional packaging, timeless

The first thing to introduce is the dual inline package (DIP). From the figure below, you can see that the IC chip using this package looks like a black centipede under the double row of contacts, which is impressive. This packaging method is the earliest IC packaging technology used. It has the advantage of low cost and is suitable for small chips that do not need to connect too many wires. However, because most of them are made of plastic, the heat dissipation effect is poor and cannot meet the requirements of current high-speed chips. Therefore, most of the chips using this package are timeless, such as the OP741 in the figure below, or IC chips that are not so demanding on operating speed and have smaller chips and fewer contacts.

The IC chip on the left is OP741, which is a common voltage amplifier. The right picture is its cross-section. This package uses gold wire to connect the chip to the metal pin (Leadframe)

As for the Ball Grid Array (BGA) package, compared with the DIP, the package size is smaller and can be easily placed in a smaller device. In addition, because the pins are located under the chip, it can accommodate more metal pins compared to DIP, which is quite suitable for chips that require more contacts. However, this packaging method is more expensive and the connection method is more complicated, so it is mostly used in high-priced products. The left picture shows a chip packaged with BGA. Most mainstream X86 CPUs use this packaging method. The right picture is a schematic diagram of BGA using flip chip packaging.

Mobile devices are on the rise, and new technologies are on the stage

However, using the above packaging methods will consume a considerable amount of volume. Mobile devices, wearable devices, etc. today require quite a variety of components. If each component is packaged independently, it will take up a lot of space when combined. Therefore, there are currently two methods that can meet the requirements of reducing volume, namely SoC (System On Chip) and SiP (System In Packet).

When smartphones first emerged, the term SoC could be found in major financial magazines, but what exactly is SoC? Simply put, it is to integrate ICs with different functions into one chip. With this method, not only can the volume be reduced, but the distance between different ICs can also be reduced, and the computing speed of the chip can be increased. As for the production method, it is to put different ICs together during IC design, and then make a mask through the design process introduced earlier.

However, SoC is not only advantageous. To design an SoC requires a lot of technical cooperation. When IC chips are packaged separately, they have external protection of the package, and the distance between ICs is far, so there is less chance of mutual interference. However, when all ICs are packaged together, it is the beginning of a nightmare. IC design factories need to change from simply designing ICs to understanding and integrating ICs with various functions, which increases the workload of engineers. In addition, many situations will be encountered, such as the high-frequency signal of the communication chip may affect ICs with other functions.

In addition, SoC also needs to obtain IP (intellectual property) authorization from other manufacturers before putting the components designed by others into SoC. Because the design details of the entire IC need to be obtained to make a complete mask to make SoC, this also increases the design cost of SoC. Some people may question why not just design one by yourself? Because designing various ICs requires a lot of knowledge related to the IC, only companies like Apple, which are rich, have the budget to poach top engineers from well-known companies to design a new IC. It is still more cost-effective to cooperate and license than to develop it by yourself.

Compromise, SiP appears

As an alternative, SiP has jumped onto the stage of integrated chips. Unlike SoC, it purchases ICs from various companies and packages them for the last time, so there is no IP licensing step, which greatly reduces the design cost. In addition, because they are independent ICs, the degree of interference between each other is greatly reduced. The most famous product using SiP technology is Apple Watch. Because the internal space of Watch is too small, it cannot use traditional technology, and the design cost of SoC is too high, so SiP has become the first choice. Through SiP technology, not only can the size be reduced, but also the distance between each IC can be shortened, becoming a feasible compromise. The following figure is the structure of the Apple Watch chip, and you can see that quite a lot of ICs are included in it.

After the packaging is completed, it is time to enter the testing stage. In this stage, it is necessary to confirm whether the packaged IC is operating normally. After it is correct, it can be shipped to the assembly plant to be made into the electronic products we see. At this point, the semiconductor industry has completed the entire production task.