Research on power electronic packaging technology and its thermal resistance determination method

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Research on power electronic packaging technology and its thermal resistance determination method [Copy link]

【Source: SMT Information Network】

Abstract: With the increasing requirements of users for power electronics cooling effect, the previous method of attaching heat sinks to power packages is difficult to implement. After introducing the process technology of power electronic devices, this paper discusses in detail the significant impact of packaging technology on power electronics, and describes the dynamic and static characteristics of power packages by taking thermally enhanced packages and thermal plug-in packages as examples, and gives the processing steps and measurement circuits for calculating thermal resistance, which has certain reference value.

Keywords: power process power package heat sink thermal resistance

Power Package and Realistic Method of Thermal Resistance Calculation　

Abstract : As users have higher demands to the result of heat sink of the power component , setting heat sinker on the power package is not easy to realize any more. The technics of power component is introduced. Then the great influence of package on power component is illustrated. This paper takes the thermal enhancement-type package and thermal tab package for examples to describe their static and dynamic characteristics. At last the measure steps and circuit of thermal resistance design are presented and have certain referential value.

Keyword: power technics power package heat sink thermal resistance

1 Introduction

Power semiconductors are increasingly used in industries, automobiles, consumer electronics, and other fields, mainly for actuators and power supply elements. With the improvement of power electronics process technology and the increasing requirements of users for heat dissipation, the previous method is difficult to implement, and the layout of the PCB has a great influence on the heat dissipation effect. In order to reduce the difficulty of PCB layout, a new method should be used to determine the thermal resistance of the power package.

2. Process Technology of Power Electronics

The level of integration (complexity) of power semiconductor products determines their product performance. Each individual product group can be optimized using dedicated technologies.

1.1 Basic process:

(1) CMOS process: CMOS (complementary MOS) only contains P-channel and N-channel, and does not include any bipolar and other devices. The transistor here is constructed by P-well and N-well and a polysilicon gate. Using polysilicon layers to form resistors, using polysilicon and doped substrates as capacitor plates, and gate oxide as dielectrics, the CMOS process is optimal for constructing logic functions. Basically, this process can manufacture a series of low-voltage devices (5V, 3V, 1.8V), achieving high integration density in extremely small components.

(2) Bipolar process: The bipolar process uses NPN and PNP bipolar transistors as active components. The bipolar process does not require polysilicon gates. This process has few steps and is cost-effective. The integration density depends on the voltage level of the process. Various voltage levels can be obtained by changing the size of the transistor.

(3) DMOS process: DMOS (double diffused MOS) transistors are optimized for high current and high voltage. In order to increase the breakdown voltage, these components are designed with a long channel structure. Several units are connected in parallel to achieve high current (low on-resistance) and high energy density. The DMOS process has a thicker gate oxide layer than the logic process, which can produce more robust devices. If these basic processes are combined in a logical way, the following different combination processes can be obtained, which can be suitable for specific application areas according to their proprietary characteristics.

(4) BC process: The BC process includes bipolar and CMOS components in one process. This combination can realize a variety of analog functions, such as high-precision reference voltage circuits.

(5) CD process: The CD process combines CMOS and DMOS components into one integrated circuit, which can combine high current, high power and logic functions into one integrated circuit.

(6) BCD process: The BCD process combines bipolar, CMOS and DMOS components to produce components with different voltage levels. CMOS allows high logic density, thereby integrating microcontrollers. The combination of bipolar and CMOS can realize high-precision reference voltage circuits. DMOS transistors make it possible to switch high currents and high voltages (up to 20A and 80V). In some cases, more than one gate oxide layer is used to achieve high integration density of low-voltage logic circuits (such as sub-micron logic), and multiple polysilicon resistive layers may be required. With advanced BCD technology, more than 25 photosensitive layers (masks) may be achieved. However, this will result in higher costs than processes such as CMOS.

1.2 Power MOSFET

Power metal oxide field effect transistors (MOSFETs) are used as switches in many cases and their analog functions are rarely used. When used as switches, they have the following different working states:

(1) When the transistor is turned off, it flows as little current as possible at the highest possible voltage. The relevant parameters are breakdown voltage and leakage current.

(2) The transistor is turned on. In this state, in order to make the current level as high as possible, the on-resistance should be as small as possible. The relevant parameters are the drain-source on-resistance and the maximum current.

(3) The switching time of the transistor turning on or off should be as short as possible to minimize the amount of charge moved. The relevant parameters are switching time, transconductance, and gate charge capacity.

Current process technologies are designed for temperatures above +200 °C . High operating temperatures are beneficial for saving silicon area and heat dissipation costs in applications. Therefore, the development trend is to increase the junction temperature, extend the life, and improve the cycle stability of active and passive devices. Other important stability parameters that must be mentioned are the impedance of radio frequency interference (EMI) and electrostatic protection (ESD).

1.3 Intelligent Field Effect Transistor (FET)

If the power MOS tube technology is enhanced by additional P-well and N-well, additional functions can be integrated into a single chip. The MOS transistor becomes an " intelligent " transistor. For example, protection and monitoring functions can be integrated. There is no bipolar structure in the resulting components, so it is called CD technology. Its feature size (that is, packaging density) is related to the thickness of the gate oxide layer and additional process steps. The smaller the feature size, the more difficult it is to manufacture and the higher the cost. In the application, low-side (LS) and high-side (HS) switches can be constructed to realize H-bridge circuits, connect loads such as DC motors, and provide bipolar voltages.

1.4 Intelligent Power Integrated Circuit

With CD technology, the chip has no analog functions and the feature size is not particularly large. This defect can be compensated by smart power technology (SPT), thereby forming an integrated circuit with a power output stage, namely a power IC (PIC), and manufacturing a free-connection power transistor. In addition to the low-side and high-side switches mentioned above, an important half-bridge circuit can also be realized in the application. It consists of two fast-turning off series MOS transistors. In addition, various analog and digital circuits such as powered CAN transceivers can also be realized.

2 Power Electronics Packaging Technology

Packaging technology is of special importance for power semiconductors. On the one hand, this is because when a device fails, it actively generates power losses and high dynamic performance. Therefore, under normal circumstances, the power loss of MOS transistors is about 1 to 2 watts, and in the event of a short circuit, the power loss will increase by more than three orders of magnitude. In this case, the chip, solder, and embedded heat sink will be in a limit working state due to the increase in heat. The second reason is that the connected wires have to flow large currents or withstand large voltages. For example, if a conventionally used cable with a cross-sectional area of 0.75 mm2 ^has the same current density as the bonding wire in the chip, then the cable needs to transmit a current of 1000A. This means that the material has reached its physical limit. Due to the progress of MOS technology, it has become possible to manufacture devices with extremely low impedance. Therefore, the power loss of the internal resistance of the package itself (bonding wires, connections between the chip and the embedded heat sink, and the embedded heat sink itself) will account for a larger proportion.

There are two types of packages for power semiconductors. The first is a heat sink surface on a chip carrier lead frame that can be soldered directly. This package has a small thermal resistance between the chip and the heat sink, called R _thj-c (thermal resistance to the case). The second is a " thermally enhanced lead frame " that connects metal leads from the chip carrier to the pins of the package. Because the molding compound hides these details,

Therefore, they cannot be distinguished from standard devices in appearance. The two different packages are described using P-T0263-15 as an example.

　The differences between these two different packages and the embedded heat sink package are described using P-T0263-15 as an example.

As the frequency continues to increase, the size of the heat sink becomes a major issue, especially when using surface mount devices (SMD). Improvements in chip technology have made it a trend to change from through-hole packaging to low-cost SMD applications. Since the printed circuit board (PCB) itself can be used as a heat sink, in many cases, " silicon semiconductors can be used instead of heat sinks . "

When calculating the PCB as a heat dissipation surface, many factors must be considered. The previous practice was to attach a solid heat sink to the power package, so that only the geometric dimensions of heat dissipation need to be considered when determining the thermal resistance, which is relatively easy to implement. However, for SMD, determining the dimensions becomes very difficult because the heat diffusion path must be analyzed: chip (connection point) - lead frame - package contact surface (container or pin) - solder hole - PCB material - PCB volume - surrounding environment. Figure 2 describes several possible ways for SMD devices to dissipate heat.

Since the PCB layout has a great influence on the heat dissipation effect in this case, a new method must be adopted. This article uses typical representatives of various packages (thermally enhanced package, thermal plug-in package) as examples to illustrate the steps of this method (the chips mentioned in this article are all power electronic products of Infineon).

2.1 Static Characteristics of Power Packaging

A power integrated circuit (PIC) consists of a chip mounted on a chip carrier using metal solder or adhesive. The circuit board is made of a good electrical conductor, such as copper, and can be several millimeters thick. Figure 3 depicts the relevant static equivalent circuit.

The power loss Pv occurs near the chip surface and is considered as a current source. The thermal resistance is considered as an ohmic resistor. In principle, the equivalent circuit is composed of a series of local thermal resistances in series. First, it is assumed that the thermal resistance of the molding compound in the parallel circuit (shown by the dotted line) can be ignored. The ambient temperature is expressed as a voltage source. By analogy, the heat flow Pv = Q/t can be calculated with the help of Ohm's theorem in thermal equivalent form:

V=I·R corresponds to T _j - T _a =Pv·R _thj-a (I ～Pv, R～R _th , V～T)

From the above formula we can obtain: Pv = -Ta _/ Rthj _-a +Tj _/ Rthj _-a , which is a descending straight line with a slope of -1/Rthj _{-a , and the zero point is at Tj} .　　　

The function corresponding to P-DSO-14-4 (thermally enhanced power package) on a standard application circuit board (PCB heat dissipation area of 400mm2) is given ^{. The power loss is a function of the ambient temperature} _Ta . From the above function, the allowable power loss at any ambient temperature can be directly derived. For example, when Ta ₌ 85 °C , the total allowable power loss Pv = (Tj _- Tmax ₎ / _Rthj-a = 65K/(92K/W) = 0

In the thermal plug package, the power loss is a function of the package temperature Tc _, because the manufacturer does not know the specific thermal resistance. As shown above, this function is still a descending straight line. In this case, the slope is -l/Rthj _-a , and the zero point is at Tj _. Taking P-T0252-3-1 (thermal plug power package) as an example, Figure 5 describes this function. It can be seen from the figure that Pvmax=30W and remains at 30W even at lower temperatures. This is due to the action of the current limiter inside the chip, which limits the increase in power loss. Therefore, at lower temperatures, the power loss value is a constant.

2.2 Dynamic characteristics of power packaging

If dynamic phenomena (pulse power mode) are considered, the thermal behavior of the PIC will change accordingly. This behavior can also be replaced by a thermal capacitance Cth, which is proportional to the material volume V (cm3 ₎ ^, density ρ (g/cm3 ⁾ , and the proportionality factor C (Ws/(g×k)) of the specific heat: Cth ₌ c ·ρ ·V=m·c. In order to calculate the heat from ΔT , the heat calculation formula in the capacitor C must be used: ΔT ·Cth ₌ P·t=Q, that is, ΔT = P·t/Cth _{, and} the power loss P represents the heat transferred per unit time.

Taking the thermal capacitance into account, the equivalent circuit of the P-T0263-7-3 power package is shown in Figure 6. The thermal capacitance calculated from the material and volume is connected in parallel with the thermal resistance.

To calculate the corresponding thermal resistance and R _th , we need to know the thickness d, the cross-sectional area A and the thermal conductivity L (W/(m·k)), and the calculation formula is as follows: R _th = d/(L·A) [K/W]. To calculate the heat capacity C _th , we need to know the volume V = d · A , density ρ (g / cm ³ ) and specific heat c (Ws/(g · k)) , so we have : C _th = m · c [K/W] .

2.3 Dynamic thermal process

Similar to the electrical system, the thermal response of the chip is considered to be the voltage rise of the RC circuit caused by the pulse current source as the excitation: V(t) = R · I · (1-e ^{t/R · C} )

Temperature rise is : T(t) = Rth _· P · (1-e t ^{/(Rth · Cth)} )

(2) At Ta ₌ 25 °C , inject a certain power loss into the device

If switch S1 _is closed, the output voltage VQ _{= 5V ,} the output current is 5/35A, and the power loss of the voltage regulator chip Pv = (V1-VQ ₎ · IQ , totaling 1W.

V _F25 = 600 mV was measured at Ta ₌ 25°C .

(3) Change Ta ₍ e.g. 85°C)

S1 _is still closed, so: Pv = 1 W. V _F85 is measured to be 400 mV.

(4) Determine Tj under the conditions of _{Ta =} 85°C, Pv = 1W, VF _{= 400 mV}

From the calibration curve, it can be determined that: T _j = 125°C.

(5) Calculation of Rthj _-a

The accurate thermal resistance value in practical applications is R _thj-a = (T _j - _Ta )/Pv , and parameters such as airflow can be changed without reducing the accuracy of the measurement. For example, R _thj-a = (125K-85K)/1W = 40K/W .

3 Conclusion

With the widespread application of power electronic devices, especially in the automotive field, the use of motor drives has increased dramatically. Currents below 10A can be provided by a monolithic integrated full-bridge chip, and large currents above 10A and below 100A require an external low-side switch. The effect of power package heat dissipation and how to determine the thermal resistance value to design or select a heat sink have become new issues. This article illustrates a method for reference, but thermal measurements are required. In addition, we can also use the finite element method for analysis, which can reduce thermal measurements and input the geometric dimensions of the package and the corresponding chip into the simulation program to determine the data required to calculate the thermal resistance.

References:

[1] Tao Wenquan . Modern Progress in Computational Heat Transfer [M] . Beijing: Science Press, 2000 .

[2] Lin Weixun . Modern Power Electronic Circuits [M] . Hangzhou: Zhejiang University Press. 2002 .

[3] Li Bingqian , Bu Liangji , Fan Guanghan . A new method for measuring thermal resistance of power LEDs [J] . Semiconductor Optoelectronics. 2003(1) : 22-24 .

[4] Wang Fupan , Yang Peng. Heat dissipation calculation of MOSFET power switch devices [J] . Communication Power Technology. 2005(1):31-33.

[5]Seri Lee , Optimum Design and Selection of Heat Sink[J] , 1995 , IEEE Tram Oil Components , Packing , and Manufacturing Technology , Part A , 1995 , 8(4) : 812-816 .

[6]Rob Blattner , Wharton McDaniel . Thermal Management in On-BoardDC-to-DCPower Conversion[R].USA:Trpes.Co.,Ltd.,1998.