How to eliminate the first current spike on the primary side of the transformer?

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How to eliminate the first current spike on the primary side of the transformer? [Copy link]

As shown in the figure above, the most common flyback power supply is used as an example. As long as the engineer who has actually tested the current waveform of the primary inductor of the switching power supply has seen a waveform like the one in the figure, a spike current will appear before the current rises linearly, and sometimes it is even higher than the normal peak current. This spike is harmful 1. It is because of the existence of this spike that the switching power supply chip adds leading edge blanking to prevent false triggering. If it is too high, it may still be falsely triggered. 2. This spike (di/dt is very large) has a significant impact on the EMI of the switching power supply. 3. This peak current will increase the crossover loss when the MOS switch is turned on, reducing efficiency 4. Customers are not happy with it, and engineers are not happy with it either So we hope it is as small as possible, preferably without it. To reduce this peak, we must know its source Let me share my views on this below. Please point out any errors. For the flyback topology, at the moment the MOS tube is turned on, there are two actual wired paths, one is the driver side, the other is the MOS drain source to the inductor, and the last one is the secondary current coupled through the transformer. 1. When the MOS tube is turned on, the driving current flows from G to S to the ground. This path has current (the driving current is limited by the driving resistor in the driving circuit, so the current is not large); 2. Another path comes down from the MOS. On the surface, this path connects the inductor. The current on the inductor is actually the main current that rises slowly from 0 (relative to the peak current). But don't forget that there is a hidden path, that is, the primary winding of the transformer has parasitic capacitance (interlayer capacitance and interturn capacitance). The electricity stored in this parasitic capacitance is instantly released from the MOS to the ground, which will generate a large peak current. 3. Another one is the current coupled from the secondary side. We all know that the secondary rectifier diode has a reverse recovery current in the process from conduction (forward bias) to reverse bias. This reverse recovery current passes through the diode and the secondary winding of the transformer, and it will be refracted to the primary winding through coupling (note: there is no reverse recovery current under DCM). Under the action of the reverse electric field, the electrons in the P region are pulled back to the N region, and the holes in the N region are pulled back to the P region, forming a reverse drift current IR, as shown in the figure below; After analysis, this peak current is composed of 3 parts: 1. Drive current (very small) 2. The instantaneous release current of the parasitic capacitance of the primary winding through the MOS 3. The reverse recovery current of the secondary diode (there is no reverse recovery current in DCM) Okay, we know that this current is mainly caused by 2 and 3, so we can prescribe the right medicine. Countermeasures 1Find a way to reduce the distributed current of the primary winding of the transformer ①Use the sandwich winding method to separate the primary winding of the transformer ②Reduce the number of turns of the primary winding (for example, you can use a magnetic core with a relatively large Ae value (PQ, etc.) to reduce the number of turns of the transformer) ③Wrap it into a single-layer winding as much as possible 2. Reduce the reverse recovery current of the secondary side ①If it is a very low-power switching power supply, design the transformer to operate in DCM mode (DCM has no reverse current). ②Use quasi-resonant chips (quasi-resonance is also in DCM) ③Use diodes with good reverse recovery characteristics, such as Schottky, and of course silicon carbide diodes. Note that silicon carbide diodes are very expensive. But no matter what, this spike cannot be completely eliminated. Summary This article mainly explains the mechanism analysis of the spike for beginners. These countermeasures are unified in some methods of improving the efficiency of switching power supplies. Even if we do not consider this peak current, we should follow: Sandwich winding method reduces leakage inductance, reduces the number of turns to reduce copper loss, and single-layer winding reduces leakage inductance; power supplies with very low power should be designed in DCM, flyback power supplies with high efficiency requirements should use quasi-resonance solutions, and output diodes should be selected with good reverse recovery characteristics to reduce diode reverse recovery losses. So we don’t need to deliberately implement these strategies specifically for this peak current Just for technical exchanges, if there are any inappropriate points, please leave a message.

asimilar

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This needs to be studied well.