Basic knowledge of TTL level, CMOS level, OC gate, OD gate

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Basic knowledge of TTL level, CMOS level, OC gate, OD gate [Copy link]

1. TTL The main type of TTL integrated circuit is transistor-transistor logic gate. Most TTL circuits use 5V power supply. 1. Output high level Uoh and output low level Uol Uoh ≥ 2.4V, Uol ≤ 0.4V 2. Input high level and input low level Uih ≥ 2.0V, Uil ≤ 0.8V 2. CMOS CMOS circuit is a voltage-controlled device with extremely large input resistance and is very sensitive to interference signals. Therefore, unused input terminals should not be open-circuited and connected to ground or power supply. The advantages of CMOS circuits are wide noise tolerance and low static power consumption. 1. Output high level Uoh and output low level Uol Uoh≈VCC, Uol≈GND 2. Input high level Uoh and input low level Uol Uih≥0.7VCC, Uil≤0.2VCC (VCC is the power supply voltage, GND is the ground) From the above, we can see that: Under the same 5V power supply voltage, COMS circuit can directly drive TTL, because the output high level of CMOS is greater than 2.0V, and the output low level is less than 0.8V; while TTL circuit cannot directly drive CMOS circuit, the output high level of TTL is greater than 2.4V, if it falls between 2.4V and 3.5V, the CMOS circuit cannot detect the high level, and the low level is less than 0.4V to meet the requirements, so when the TTL circuit drives the COMS circuit, a pull-up resistor needs to be added. If there is a different voltage power supply, it can also be judged by the above method. If a 3.3V COMS circuit drives a 5V CMOS circuit, such as a 3.3V microcontroller driving a 74HC, there are several ways to solve this problem. The simplest way is to directly replace the 74HC with a 74HCT chip (the input and output of the 74 series are introduced below), because the 3.3V CMOS can directly drive a 5V TTL circuit; or add a voltage conversion chip; another way is to set the I/O port of the microcontroller to open drain, and then add a pull resistor to 5V. In this case, the size of the resistor must be adjusted according to the actual situation to ensure the rising edge time of the signal. 3. Introduction to 74 series 74 series can be said to be the chip we usually come into contact with the most. There are many types in the 74 series, and the ones we usually use the most should be the following: 74LS, 74HC, 74HCT. The differences in the levels of these three series are as follows: Input level Output level 74LS TTL level TTL level 74HC COMS level COMS level 74HCT TTL level COMS level ++++++++++++++++++++++++++++++++++++++++ TTL and CMOS level 1. TTL level (what is TTL level): Output high level>2.4V, output low level<0.4V. At room temperature, the general output high level is 3.5V, and the output low level is 0.2V. Minimum input high level and low level: input high level>=2.0V, input low level<=0.8V, and the noise tolerance is 0.4V. 2. CMOS level: 1 logic level voltage is close to the power supply voltage, and 0 logic level is close to 0V. And it has a very wide noise tolerance. 3. Level conversion circuit: Because the high and low level values of TTL and COMS are different (ttl 5v <==>cmos 3.3v), level conversion is required when connecting to each other: that is, use two resistors to divide the level, nothing profound. 4. OC gate, that is, collector open gate circuit, OD gate, that is, drain open gate circuit, must have external pull-up resistors and power supply to use the switch level as high and low levels. Otherwise, it is generally only used as a switch for large voltage and large current loads, so it is also called a drive gate circuit. 5. Comparison between TTL and COMS circuits: 1) TTL circuits are current-controlled devices, while CMOS circuits are voltage-controlled devices. 2) TTL circuits are fast and have short transmission delays (5-10ns), but they consume a lot of power. COMS circuits are slow and have long transmission delays (25-50ns), but they consume a lot of power. The power consumption of the COMS circuit itself is related to the pulse frequency of the input signal. The higher the frequency, the hotter the chipset, which is normal. 3) Locking effect of COMS circuit: Due to the input of too much current, the internal current of COMS circuit increases sharply. Unless the power is cut off, the current keeps increasing. This effect is called locking effect. When the locking effect occurs, the internal current of COMS can reach more than 40mA, which can easily burn the chip. Defensive measures: 1) Add clamping circuits at the input and output ends to prevent the input and output from exceeding the specified voltage. 2) Add decoupling circuits to the power input end of the chip to prevent instantaneous high voltage at the VDD end. 3) Add a current limiting resistor between VDD and the external power supply to prevent it from entering even if there is a large current. 4) When the system is powered by several power supplies, the switches should be in the following order: when turned on, turn on the COMS circuit power supply first, then turn on the input signal and load power supply; when turned off, turn off the input signal and load power supply first, then turn off the COMS circuit power supply. 6. Precautions for the use of COMS circuits 1) COMS circuits are voltage-controlled devices, and their input total impedance is very large, and they have a strong ability to capture interference signals. Therefore, do not leave unused pins floating, but connect pull-up or pull-down resistors to give it a constant level. 2) When the input terminal is connected to a low-resistance signal source, a current-limiting resistor should be connected in series between the input terminal and the signal source to limit the input current to within 1mA. 3) When connecting a long signal transmission line, connect a matching resistor to the COMS circuit terminal. 4) When a large capacitor is connected to the input terminal, a protective resistor should be connected between the input terminal and the capacitor. The resistance value is R=V0/1mA. V0 is the voltage on the external capacitor. 5) If the input current of COMS exceeds 1mA, it may burn out COMS. 7. Input load characteristics in TTL gate circuits (handling of special cases with resistors at the input terminal): 1) When floating, it is equivalent to a high level at the input terminal. Because at this time, it can be regarded as an infinite resistor connected to the input terminal. 2) After a 10K resistor is connected in series at the input terminal of the gate circuit and a low level is input, the input terminal presents a high level instead of a low level. Because from the input load characteristics of the TTL gate circuit, only when the series resistance connected to the input terminal is less than 910 ohms, the low-level signal inputted can be recognized by the gate circuit. If the series resistance is larger, the input terminal will always be at a high level. This must be paid attention to. The COMS gate circuit does not need to consider these. 8. The TTL circuit has an open collector OC gate, and the MOS tube also has an open drain OD gate corresponding to the collector. Its output is called an open drain output. The OC gate has a leakage current output when it is cut off, which is the leakage current. Why is there a leakage current? That is because when the transistor is cut off, its base current is approximately equal to 0, but it is not really 0, and the current passing through the collector of the transistor is not really 0, but about 0. And this is the leakage current. Open drain output: The output of the OC gate is an open drain output; the output of the OD gate is also an open drain output. It can absorb a large current, but cannot output current to the outside. Therefore, in order to input and output current, it must be used together with a power supply and a pull-up resistor. OD gates are generally used as output buffers/drivers, level converters, and to meet the needs of absorbing large load currents. 9. What is a totem pole, and how is it different from an open-drain circuit? In TTL integrated circuits, the output with a pull-up transistor is called a totem pole output, and the output without a pull-up transistor is called an OC gate. Because TTL is a three-level switch, the totem pole is two transistors connected in push-pull mode. So push-pull is a totem. Generally, the totem output is 400UA for high level and 8MA for low level. +++++++++++++++++++++++++++++++++++++++++++++++++ The unused input terminals of CMOS devices must be connected to high or low level, because CMOS is a high input impedance device, and ideally there is no input current. If the unused input pins are left floating, it is easy to sense interference signals, affecting the logic operation of the chip, and even static electricity accumulation will permanently break down the input terminal, causing the chip to fail. In addition, only 4000 series CMOS devices can work under 15V power supply, 74HC, 74HCT, etc. can only work under 5V power supply, and now there are CMOS logic circuit chips that work under 3V and 2.5V power supply.CMOS level and TTL level: The range of CMOS logic level is relatively large, ranging from 3 to 15V. For example, when the 4000 series is powered by 5V, the output is high when it is above 4.6V and low when it is below 0.05V. The input is high when it is above 3.5V and low when it is below 1.5V. For TTL chips, the power supply range is 0 to 5V, and 5V is common. For example, the 74 series is powered by 5V, the output is high when it is above 2.7V and low when it is below 0.5V. The input is high when it is above 2V and low when it is below 0.8V. Therefore, there is a level conversion problem between CMOS circuits and TTL circuits, so that the level domain values of the two can match. Some concepts about logic levels: To understand the content of logic levels, you must first know the meaning of the following concepts: Input high level (Vih): The minimum input high level allowed when the input of the logic gate is high. When the input level is higher than Vih, the input level is considered to be high. Input low level (Vil): The maximum input low level allowed when the input of the logic gate is at a low level. When the input level is lower than Vil, the input level is considered to be a low level. Output high level (Voh): The minimum output level when the output of the logic gate is at a high level. The level value when the output of the logic gate is at a high level must be greater than this Voh. Output low level (Vol): The maximum output level when the output of the logic gate is at a low level. The level value when the output of the logic gate is at a low level must be less than this Vol. Threshold level (Vt): Digital circuit chips all have a threshold level, which is the level at which the circuit can just barely flip the action. It is a voltage value between Vil and Vih. For the threshold level of CMOS circuits, it is basically half the power supply voltage value, but to ensure stable output, it is necessary to require the input high level > Vih and the input low levelVih > Vt > Vil > Vol Ioh: Load current when the logic gate output is high (source current). Iol: Load current when the logic gate output is low (sink current). Iih: Current when the logic gate input is high (sink current). Iil: Current when the logic gate input is low (source current). The output of the gate circuit is not connected to a load resistor in the integrated unit but is directly led out as the output terminal. This type of gate is called an open gate. The open TTL, CMOS, and ECL gates are called open collector (OC), open drain (OD), and open emitter (OE) respectively. When using, you should check whether to connect a pull-up resistor (OC, OD gate) or a pull-down resistor (OE gate), and whether the resistance value is appropriate. For an open collector (OC) gate, the pull-up resistor RL should satisfy the following conditions: (1): RL < (VCC-Voh)/(n*Ioh+m*Iih) (2): RL > (VCC-Vol)/(Iol+m*Iil) Where n: the number of open gates of the line-AND; m: the number of driven input terminals.