Implementation of an Anti-interference Filter Based on EPLD Technology

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Implementation of an Anti-interference Filter Based on EPLD Technology [Copy link]

【Abstract 】A flexible and simple anti-interference filter is designed using the ispLSI1032E in-circuit programmable device from Lattice.　
Keywords : Programmable logic device, filter, anti-interference
　
1 Problem statement:
　　In the process of synchronous serial data transmission, any small burr on the clock line will cause data transmission errors, thus affecting the normal operation of the system. The traditional processing method is to add a small capacitor to the receiving end to filter out the burr. This method can only remove the interference at a fixed frequency. In actual work, the interference may be generated by a mixture of multiple interference sources, and its frequency may be variable. In addition, if there are multiple receiving ends for synchronous serial transmission, a capacitor needs to be added to each receiving line. In this way, multiple capacitors are connected in parallel on the same signal line, which will inevitably cause the required signal to be distorted. With the development of modern electronic technology, EPLD has become one of the important means of modern electronic design due to its flexible and convenient programming. This paper introduces a digital filter based on EPLD, which can suppress interference on certain low-frequency lines. This filter can prevent interference signals in certain frequency bands from passing through, thereby playing the role of hardware anti-interference. Due to the use of EPLD technology, hardware programming is convenient and flexible, and corresponding measures can be taken to solve the characteristics of different interference sources.
2 Solutions
　　Serial transmission lines are prone to interference during actual transmission, which is usually in the form of small glitches or narrow pulses. They can be filtered out by using their different characteristics from the main signal.
2.1 Basic working principle
　　To eliminate interference signals, two input signals are required: the main signal and the reference clock signal. The reference clock signal is processed by frequency division and pulse width adjustment to make the main signal source produce the required delay, and then compared with its own signal, some narrow-wave interference signals on the main signal source are filtered out. The schematic diagram of the filter is shown in Figure 1. The device can be ispLSI1032E from LATTICE, and the reference clock signal can be an 8M crystal oscillator.
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2.2 Specific circuit design
　　The programming software is ispEXPERTSystem from LATTICE, which is a complete set of digital system design software. The design input can be in the form of schematic input, hardware description language input, mixed input, etc., and the designed digital circuit system can be functionally simulated and timing simulated.
2.2.1 Frequency division circuit
　　The frequency division circuit can be determined according to the pulse width of each specific interference source. The specific circuit is shown in Figure 2. CLK is an 8M crystal oscillator signal, which is used as the trigger signal of the DQ trigger after shaping. OUT1 outputs a 4M square wave signal after two-frequency division. At the same time, as the clock signal of the next-level trigger, OUT2 outputs a 2M square wave signal after four-frequency division. FW1 outputs a pulse signal with a frequency of 4M and a pulse width of 125ns, and FW2 outputs a pulse signal with a frequency of 2M and a pulse width of 250ns. The specific waveform is shown in Figure 3. By analogy, continuing to cascade DQ triggers can output eight-frequency division and sixteen-frequency division signals, and the pulse width can also be changed accordingly depending on the specific situation. The circuit is similar to the generation circuit of FW1 and FW2.
From Figure 2, the waveform shown in Figure 3 is obtained by simulation in ispEXPERT.
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2.2.2 Delay Circuit
　　According to the interference source, the above-mentioned signal is used as the trigger clock, and the unprocessed signal source is triggered to generate a delay, and then compared with itself. In this way, some interference signals are filtered out due to their narrow pulse width. The specific circuit is shown in Figure 4.

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　　SIGNIN is the signal to be processed. After being triggered by the first trigger, a delay is generated and it is sent to the secondary trigger to generate a secondary delay. The frequency of the CLKIN signal depends on the width of the interference source, but it should be noted that the width of the interference source must be much smaller than the width of the signal source, otherwise the signal width will be greatly reduced, resulting in the destruction of the characteristics. The circuit simulation waveform is shown in Figure 5.
　　On the SIGNIN signal line, the second pulse is filtered out because its width is smaller than the CLKIN signal period. This is particularly important on the clock line of synchronous serial transmission.
3 Effect Analysis
This circuit is simple and reliable. The author used this circuit to solve the interference problem in a serial synchronous communication process and achieved good results.
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Because it is based on EPLD technology, no additional hardware is required, and the programming is flexible. It can be directly simulated in ispEXPERT, saving a lot of experimental time. However, two points should be noted in actual operation: First, when using this filter, the main signal pulse will have a certain delay. As a synchronous clock, this delay will not have much impact on serial communication, but if it is used on data lines or other signal lines, the impact of the delay time on the system must be considered; second, when using ispEXPERTSystem for programming, the macro device function it provides is similar to that of TTL devices, but individual pins are different. In addition, the above principles can be used to promote the application of interference on various transmission lines.

　　
　References　　

1 Wang Xiaojun. VHDL Concise Tutorial. Beijing: Tsinghua University Press, 1997