How to achieve zero-defect manufacturing of automotive electronic components with the help of PAT testing

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How to achieve zero-defect manufacturing of automotive electronic components with the help of PAT testing [Copy link]

The industry's call for zero-defect semiconductor components is growing, and semiconductor manufacturers are beginning to invest more to meet the challenge and meet the needs of automotive users. As the number of electronic components in automobiles continues to increase, the quality of semiconductor components in modern automobiles must be strictly controlled to reduce the defect rate per million parts (DPM), minimize field returns and warranty issues related to electronic components, and reduce liability issues caused by electronic component failures. The

American Automotive Electronics Council AEC-Q001 specification recommends a general method that uses the Part Average Testing (PAT) method to eliminate abnormal parts from the total parts, thereby improving the quality and reliability of components at the supplier stage. For a specific wafer, batch number, or group of parts to be tested, the PAT method can indicate the test results where the total average falls outside 6σ. Any test result that exceeds the 6σ limit value for a specific component is considered unqualified and is eliminated from the total number of parts. Parts that do not meet the PAT limit value cannot be shipped to customers, which improves the quality and reliability of components.

User requirements for these specifications have led to more intense competition among suppliers. There is great pressure to improve reliability and reduce defect rates, especially for many critical safety functions now controlled by semiconductors, such as brakes, traction control, powertrain and active stability control systems. Suppliers must improve the quality of parts that are already shipping while minimizing the impact of these specifications on their yields. As manufacturing costs continue to fall while test costs remain relatively unchanged, test costs are becoming an increasing proportion of manufacturing costs and component profit margins continue to shrink. Since the vast majority of yields cannot meet requirements, suppliers must thoroughly evaluate their test procedures to find alternative test methods and iterate through the alternative methods until the best method is found.

Without the help of cutting-edge analysis and simulation tools, suppliers will apply these specifications without fully understanding the impact they will have on the supply chain. Even worse, if they are blindly applied and important tests are omitted, the result is that even if the component is tested to a specification such as PAT and shipped at the same DPM rate, the guarantee is meaningless in this case and reliability will be reduced.

Some suppliers seem to think that PAT testing during wafer probing is sufficient, but research shows that there are many problems with this approach. PAT during wafer probing is the first quality checkpoint, but the increased variability caused by the myriad variables in the remaining downstream manufacturing processes will lead to more PAT outliers during package test. If suppliers want to release high-quality parts, they must perform PAT testing at both wafer probing and final test, and their customers should also promote the use of this approach.

Real-time PAT and statistical post-processing The PAT process uses an approach that analyzes the latest data from several batch processes and establishes static PAT limits for each test of interest. These limits are calculated to average +/-6σ and are usually integrated into the test program as upper specification limits (USL) and lower specification limits (LSL). Static PAT limits must be reviewed and updated at least every six months.

The preferred approach is to calculate dynamic PAT limits for each batch or wafer. Dynamic PAT limits are usually more stringent than static PAT limits and eliminate any outliers that are not within the normal distribution. The most important difference is that dynamic PAT limits are calculated per wafer or batch, so the limits will change continuously based on the material properties used in the wafer or batch. Dynamic PAT limits are calculated as mean +/- (n*σ) or median +/- (N*toughnessσ) and cannot be less than the LSL or greater than the USL specified in the test procedure. The

calculated PAT limits must be used as the lower PAT limit (LPL) and upper PAT limit (UPL) shown in Figure 1. Any value that exceeds the dynamic PAT limit and is between the LSL and USL limits is considered an outlier. These outliers are usually named as failures and are packaged into a specific outlier software and hardware box. Tracking the calculated PAT limits for a specific wafer or batch and the number of outliers detected for each test is important for later traceability. There are two main methods for implementing PAT: real-time PAT and statistical post-processing (SPP). Suppliers must understand whether to use two different methods for detection and final test, or whether it makes more sense to use only one approach.

Real-time PAT makes sorting decisions as the parts are tested, based on the calculation of dynamic PAT limits, without affecting test time. This requires a dynamic real-time engine that can handle complex data streams for monitoring and sampling. Similarly, this process also requires a robust statistical engine that can capture test data and perform the necessary calculations to generate new limits, feed the new limits and sorting information into the test program; at the same time, monitor the entire process to ensure stability and controllability. Suppliers need to perform real-time processing for probing and final test and handle baseline outliers.

Statistical post-processing methods produce the same final test results. After a batch is completed, the component test is statistically processed and sorting decisions are made. However, because the sorting decision is made after the batch is processed, post-processing can only be used for wafer probing, because the test and sorting results are related to specific components for re-sorting. In package test, once the components are packaged, there is no way to track or sequence them, so there is no way to associate test and sorting results with specific components. SPP also requires data logging of complete test results in order to make decisions, which the increasing IT infrastructure requires (a lot of time) and significantly slows down test time. Since the results are post-processed, SPP treats baseline outliers in a batch as part of the component as a whole.

Both methods require powerful calculations to be performed when processing test and sorting results, just like regional PAT and other failure modes. An example of regional PAT is a good die surrounded by multiple failed die in a wafer. Studies have shown that this good component is likely to fail prematurely, and most suppliers must find this good component in order to work hard to reduce DPM in automotive components.

Real-time test implementation Assume that at this moment we are manufacturing power management components for automobiles. We load historical test data into analysis tools and perform in-depth analysis of component parameter data to find which test is a good candidate for PAT. There are good and bad tests, some are more suitable for PAT, and some are more important for functional testing of components. If all tests for the component are selected, the yield will be unacceptable.

The problem with some tests is that the data is not stable enough to be measured against the PAT standard. This variability may be inherent in the component itself, introduced by the test process (e.g. an instrument in an automated measurement machine cannot produce accurate measurements), or introduced by the packaging process, which happens not to be statistically controlled and cannot be measured.

Baselines are used to establish dynamic PAT limits for a particular wafer or lot. For example, on a wafer containing 1,000 die, a baseline of 100 typical die would be the most appropriate statistical sampling for that wafer.

Once a baseline is reached, several important tasks need to be performed before dynamic PAT limits are applied in a live environment. A normality check is performed on each selected test. If the data is normally distributed, the standard deviation is calculated using the 'normal' method; however, if the data is not normally distributed, the standard deviation is calculated using the 'robust' method.

Dynamic PAT limits for each selected test must be calculated and stored in memory for subsequent testing. The initial LSL and USL remain unchanged and are used to detect test failures according to the original test procedure. Baseline outliers are calculated for the selected tests. In probing, XY coordinates are saved for processing after wafer fabrication. In package test, baseline components are sorted into baseline bins. If outliers in the baseline are detected, then those components are identified for retesting.

Once the baseline is reached, dynamic PAT limits are checked for each selected test and each component is binned in real time. Components that do not meet the PAT limits fall into a unique ‘outlier’ software or hardware bin that identifies them as PAT outlier components for post-testing.

The best part of a real-time system is the ability to process feedback in real time as components are tested, triggering actions and alerting personnel. For example, if the total number of outliers in the baseline exceeds the user-entered limit, a trigger is activated and alerts the test personnel to retest the baseline binned parts at package test. In a real

-time environment, outliers in the statistical baseline must be post-processed after the production batch is executed. This is not an issue in an SPP environment because all data is processed simultaneously after the production batch is completed. Even though the actual number of outliers is usually small, it is still important to handle outliers in the baseline components. Although both PAT approaches have their merits, the fastest path to meeting reliability requirements without interrupting the test process is through real-time, proactive quality management based on sound statistical methods.

Scott Bibbee

Marketing Director, Pintail Technologies