About the storage operation of EPCS configuration chip in NIOS II soft core

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About the storage operation of EPCS configuration chip in NIOS II soft core [Copy link]

The video image overlay board made with CYCLONE FPGA needs to store some user configuration information. In addition to storing FPGA configuration information and NIOS II programs, the EPCS4 configuration chip also has a lot of unused storage space, which can be used to store user configuration information. Regarding the post about CPCS device operation under NIOS II, it took him more than a month to figure out how to operate it, and then he gave a simple example. As he posted Let's take a look at this simple program first #include#include #include "system.h" #include "alt_types.h" #include "sys/alt_flash.h" #include "sys/alt_flash_dev.h" alt_u8 epcsbuf[32]; int ret_code; [ size=4]alt_flash_fd* my_epcs;//Define handle main() { my_epcs = alt_flash_open_dev("/dev /epcs_controller");//Open the FLASH device and get the handle ret_code = alt_epcs_flash_get_info (my_epcs, ions, &number_of_regions);//Get configuration chip information if(my_epcs) //Information obtained successfully { [size =4] //example application, read general data from epcs address 0x70000 ret_code = alt_epcs_flash_erase_block(my_epcs, regions->offset+0x70000);//Erase the 8th block [ size=4]ret_code = alt_epcs_flash_write(my_epcs, regions->offset+0x70000, epcsbuf, 32); //Write 32 bytes ret_code = alt_epcs_flash_read(my_epcs, regions->offset+0x70000, epcsbuf, 32); //Read 32 bytes } while(1) { } } The above program is the process and method of operating the EPCS configuration chip. First, open the device and obtain the handle my_epcs , and then the read, write and erase operations are all operated through the handle my_epcs. The "epcs_controller" in "/dev/epcs_controller" is named by the user when configuring the NIOS core, which can be found in system.h, that is, "EPCS_CONTROLLER_NAME". You can view the FLASH related parameters pointed to by my_epcs through IDE debugging. EPCS devices have only one region (regions), and there are 8 blocks (blocks) in the EPCS4 region, each block is 65536 bytes. (Note: Only EPCS1 has 32768 bytes per block, and the rest of the configuration chips have 65536 bytes per block.) alt_epcs_flash_erase_block(my_epcs, regions->offset+0x70000); // Erase 8th This function is used to erase the entire block. The first parameter is the handle just obtained, which is used to indicate that the FLASH just opened is to be erased. The second parameter is regions->offset. The value is actually 0, which is managed by the EPCS control module itself. The FPGA configuration file and the program in the NIOS core are stored from the front, that is, from the address starting from regions->offset+0x00000. I used less than 4 Blocks, there are 4 blocks left for custom storage. To facilitate future functional expansion, try to keep low blocks free for future use, and give priority to using high address space (block 8, starting address is regions->offset+ 0x70000) to store user configuration information. alt_epcs_flash_write(my_epcs, regions->offset+0x70000, epcsbuf, 32); //Write 32 bytes Write the continuous 32 bytes in the epcsbuf array If the address is 0x100 in block 6, then regions->offset+0x60100 can be used instead of regions->offset+0x70000. 4] alt_epcs_flash_read(my_epcs, regions->offset+0x70000, epcsbuf, 32); //Read 32 bytes Read continuous data from the starting point of the 8th segment in EPCS4 regions->offset+0x70000 32 bytes are stored in the epcsbuf array. During debugging, you can manually modify the values in the epcsbuf array before executing alt_epcs_flash_write, and change the values in the epcsbuf array to other values before executing alt_epcs_flash_read. If the values in the epcsbuf array are restored after executing alt_epcs_flash_read, To the value before executing alt_epcs_flash_write, the read and write operations on the EPCS chip have been successful.