Misunderstanding 1: The PCB design requirements of this board are not high, so just use thinner wires and do automatic routing
Comments: Automatic routing will inevitably occupy a larger PCB area and produce many times more vias than manual routing. In large-volume products, the factors that PCB manufacturers consider for price reduction, in addition to business factors, are line width and the number of vias. They affect the PCB yield and the number of drill bits consumed, respectively, saving the supplier's cost, and finding a reason for price reduction.
Misconception 2: It will be more reassuring if you use resistors to pull bus signals
Comment : There are many reasons why signals need to be pulled up and down, but not all of them need to be pulled up. When a simple input signal is pulled up and down by a pull-up resistor, the current is less than tens of microamperes, but when a driven signal is pulled up, the current will reach the milliampere level. The current system often has 32 bits of address data each, and there may be 244/245 isolated buses and other signals. If all are pulled up, several watts of power consumption will be consumed by these resistors.
Misconception 3: How to deal with the unused I/O ports of CPU and FPGA? Leave it empty first and talk about it later
Comment : If the unused I/O port is left floating, it may become an input signal that oscillates repeatedly due to a little interference from the outside world, and the power consumption of MOS devices basically depends on the number of flips of the gate circuit. If it is pulled up, each pin will also have a microampere current, so the best way is to set it as an output.
These FPGAs that cannot be used can be used to their full potential
Comment: The power consumption of FGPA is proportional to the number of triggers used and the number of flip-flops, so the power consumption of the same model of FPGA at different times in different circuits may differ by 100 times. Minimizing the number of high-speed flip-flops is the fundamental way to reduce FPGA power consumption.
Misunderstanding 4: Not considering small chips with very low power consumption
Comment: It is difficult to determine the power consumption of chips with less complex internal components. It is mainly determined by the current on the pins. An ABT16244 consumes less than 1 mA without a load, but its indicator is that each pin can drive a 60 mA load, that is, the maximum power consumption at full load can reach 60*16=960mA. Of course, the power supply current is so large that the heat falls on the load.
Misconception 5: The memory only needs OE and WE signals, the chip select is grounded, and the data will come out quickly
Comment: The power consumption of most memories will be more than 100 times greater when the chip select is valid than when the chip select is invalid, so CS should be used to control the chip as much as possible, and the width of the chip select pulse should be shortened as much as possible while meeting other requirements.
Misconception 6: As long as the matching is good, all overshoots can be eliminated
Comment: Except for a few specific signals, all have overshoots. As long as they are not very large, they do not necessarily need to be matched. Even if they are matched, they do not have to be matched to the best. Generally, the output impedance of the signal is not the same when it outputs high level and low level, and there is no way to achieve complete matching. Therefore, for the matching of TTL, LVDS, 422 and other signals, it is sufficient to make the overshoot acceptable.
Myth 7: Reducing power consumption is only related to hardware, not software
Comment: Almost every chip access and every signal flip on the bus is controlled by software. If the software can reduce the number of external memory accesses, respond to interrupts in a timely manner, and take other specific measures for specific boards, it will make a great contribution to reducing power consumption.
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