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Chapter 1 Overview 1 1.1 Examples of low-speed design and high-speed design 1 [Case 1-1] Simplified storage circuit module 1 1.1.1 Low-speed design 1 1.1.2 High-speed design 2 1.2 How to distinguish between high speed and low speed 3 1.3 Hardware design process 5 1.3.1 Requirements analysis 6 1.3.2 Outline design 7 1.3.3 Detailed design 7 1.3.4 Debugging 9 1.3.5 Testing 9 1.3.6 Production conversion 10 1.4 Schematic design 11 Chapter 2 Selection and application of resistors, capacitors, inductors and magnetic beads in high-speed circuits 13 2.1 Application of resistors 13 2.1.1 Classic cases related to resistors 13 [Case 2-1] 2.2.2 The role and analysis of capacitors in high-speed circuit design 19 [Case 2-7] Improper selection of AC coupling capacitors causes data frame errors 20 [Case 2-8] Using capacitors in 0612 packages to enhance filtering performance 21 [Case 2-9] ESR issues of filter capacitors in LDO power supply applications 22 [Case 2-10] 1F in high-frequency circuits Can +0.01F widen the low impedance frequency band? 24 2.2.3 Commonly used capacitors in high-speed circuit design and their application points 26 [Case 2-11] Wrong selection of ceramic capacitors leads to data packet loss on the board 27 [Case 2-12] Selecting tantalum capacitors according to circuit requirements 29 2.2.4 Decoupling capacitors and bypass capacitors 31 2.3 Selection and application of inductors 32 2.3.1 Classic cases related to inductors 32 [Case 2-13] LC low-pass filtering causes large output power supply voltage ripple 32 [Case 2-14] PI-type filtering in large current paths causes voltage attenuation 33 2.3.2 The role of inductors in high-speed circuit design 35 2.3.3 Commonly used inductors in high-speed circuit design and their application points 36 2.4 Selection and application of magnetic beads 39 2.4.1 Filtering mechanism of magnetic beads 39 2.4.2 Selection and application of magnetic beads in high-speed circuit design 40 【Case 2-15】 Misuse of magnetic beads causes failure of overcurrent protection circuit 41 2.4.3 Comparison of magnetic beads and inductors 42 Chapter 3 Selection of logic devices in high-speed circuits and application of high-speed logic levels 44 3.1 Classic cases related to logic devices 44 【Case 3-1】 The pull-up of the logic device input is too weak, causing the live plug-in monitoring function to fail 44 3.2 Key points for logic device application 47 3.2.1 Overview of logic devices 47 【Case 3-2】 Excessive driving capability of logic devices causes signal ringing 51 【Case 3-3】 Differences in logic devices of the same model cause PHY configuration errors 51 3.2.2 Introduction to logic device parameters 52 3.2.3 Calculation of power consumption of logic devices 60 3.2.4 Introduction to hot-swap function of logic devices 62 3.2.5 Summary of precautions when using logic devices 68 3.3 Application of high-speed logic levels 68 3.3.1 Overview of high-speed logic levels 68 【Case 3-4】 3.3.2 Introduction to LVDS logic levels and key points of its application 71 [Case 3-5] Improper processing of idle input pins causes FPGA to detect incorrect input 73 3.3.3 Introduction to LVPECL logic levels and key points of its application 75 3.3.4 Introduction to CML logic levels and key points of its application 77 3.3.5 Comparison of high-speed logic levels 78 3.3.6 Interconnection of high-speed logic levels and key points of its application 78 Chapter 4 Power Supply Design in High-Speed Circuits 87 4.1 Classic Cases Related to Power Supply 87 [Case 4-1] The output power supply level of LDO is lower than the set value 87 [Case 4-2] The undervoltage protection circuit of the power supply chip causes the power-on timing to fail to meet the design requirements 88 [Case 4-3] Voltage balancing measures when multiple power modules work in parallel 89 4.2 Power Supply Architecture for High-Speed Circuit Design 90 4.2.1 Centralized Power Supply Architecture 90 4.2.2 Distributed Power Supply Architecture 90 4.3 4.3.1 Introduction to LDO power supply and its application points 92 [Case 4-4] Calculation of junction temperature of LDO during operation 95 [Case 4-5] SENSE function causes unstable output voltage of power supply chip 97 4.3.2 Introduction to DC/DC power supply and its application points 100 [Case 4-6] Calculation of gate current 105 [Case 4-7] MOSFET damage caused by simultaneous conduction 108 [Case 4-8] MOSFET burnout in -48V slow-start circuit 111 [Case 4-9] Monitoring of multiple power supplies based on ADM1066 114 [Case 4-10] Control of power-on speed based on LTC1422 115 [Case 4-11] Control of power-on speed based on power supply chip 115 [Case 4-12] Delay function based on RC resistor-capacitor circuit 116 [Case 4-13] Excessive power-on current causes inductor whistling 116 [Case 4-14] 4.3.3 Power Management 124 4.3.4 Fuse Selection and Application 124 [Case 4-15] Fuse Selection for Hot-Swap Boards 126 Chapter 5 Timing Design in High-Speed Circuits 127 5.1 Timing Design Overview 127 5.2 Timing Parameter Introduction 127 5.3 Timing Design in Source Synchronous Systems 129 5.3.1 Timing Design Principles for Source Synchronous Systems 129 5.3.2 Timing Design Example 1 for Source Synchronous Systems 131 5.3.3 Timing Design Example 2 for Source Synchronous Systems 134 5.4 Timing Design in Common Clock Systems 136 5.5 Comparison between Source Synchronous Systems and Common Clock Systems 137 Chapter 6 Reset and Clock Design in High-Speed Circuits 139 6.1 Reset Circuit Design 139 6.1.1 Classic Cases Related to Reset Circuits 139 [Case 6-1] The main control board cannot query the interface board through the PCI-X bus 139 6.1.2 Introduction to reset design and its application points 141 [Case 6-2] Error in reading the storage module 141 6.1.3 Use of dedicated reset chip 142 6.2 Clock circuit design 145 6.2.1 Classic cases related to clock circuits 145 [Case 6-3] The problem of the system clock being too fast 145 [Case 6-4] The problem of being unable to read the PHY register 147 [Case 6-5] The problem of packet loss in high-temperature traffic test 148 6.2.2 Introduction to crystals and crystal oscillators and their application points 150 [Case 6-6] Using the first clock edge to start the combinational logic causes the CPU to work unstably 153 6.2.3 Phase-locked loop and its application 157 [Case 6-7] The application of a two-stage phase-locked loop causes the PCI clock of MPC8280 to lose lock 162 6.2.4 Clock jitter and phase noise 164 Chapter 7 Memory Application and Design in High-Speed Circuits 172 7.1 Classic Cases Related to Memory 172 [Case 7-1] Insufficient Timing Margin Leads to Memory Test Error 172 7.2 Introduction to Common Memory and Key Points of Its Application 174 7.2.1 Memory Overview 174 7.2.2 Introduction to SDRAM and Key Points of Its Application 176 7.2.3 Introduction to DDR SDRAM and Key Points of Its Application 188 [Case 7-2] DLL Defects Cause DDR SDRAM Timing Error 192 [Case 7-3] VREF Unstable Causes Memory Read and Write Operation Errors 198 7.2.4 Introduction to DDR2 SDRAM and Key Points of Its Application 203 [Case 7-4] Problem of CPU Storage System Not Being Able to Identify 8-bit Memory 211 7.2.5 Introduction to SRAM and Key Points of Its Application 212 [Case 7-5] Improper Chip Select Processing Leads to SRAM Data Loss 214 7.2.6 Introduction to FLASH and EEPROM 227 [Case 7-6] Hot Swapping Leads to Damage to Single Board FLASH 227 [Case 7-7] Error in Reading 100M Optical Module Information 231 Chapter 8 PCB and Integrity Design in High-Speed Circuits 232 8.1 Classic Cases Related to PCB and Integrity Design 232 [Case 8-1] Impact of Return Path Defects on High-Speed Signal Quality 232 8.2 PCB Stacking Structure and Impedance Calculation 234 8.2.1 Core and PP 234 8.2.2 PCB Stacking Structure and Impedance Design 234 8.3 Key Points of High-Speed Circuit PCB Design 241 8.3.1 PCB Design and Signal Integrity 241 【Case 8-2】 Determination of transmission lines 241 【Case 8-3】 Calculation of reflection 242 【Case 8-4】 Selection of the placement position of the terminal resistor RTT in DDR SDRAM design 244 【Case 8-5】 Crosstalk of large drive current signals on high-speed data signals 250 【Case 8-6】 Excessive radiation caused by batch replacement of high-speed interface components 252 【Case 8-7】 TCK signal back-grooving causes inability to load CPLD through the JTAG interface 256 8.3.2 PCB design and power integrity 257 8.3.3 EMC in PCB design 260 【Case 8-8】 Radiation problems caused by the signal line of the network port indicator light 264 【Case 8-9】 The interface chip and the clock driver share the same power supply, resulting in excessive radiation 266 8.3.4 ESD protection in PCB design 267 【Case 8-10】 Improper placement of the TVS tube leads to failure of the electrostatic discharge test 268 【Case 8-11】 Mixing GND and HV_GND causes power control circuit failure 270 8.3.5 PCB design, structure and usability 272 [Case 8-12] The order of the network port indicator lights is wrong 273 [Case 8-13] Network port connector stacking method and easy plug-in characteristics 273 8.3.6 PCB design and heat dissipation 274 8.3.7 PCB design and testability 275 References 279 Click to download: High-speed circuit design practice

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