Files involved when CoreGen works

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Files involved when CoreGen works [Copy link]

CoreGen involves the following files when working: 1. Project file CGP file: CoreGen project file, which stores user-defined parameters. 2. Input file CGF file: It is a log file that records user-defined input to generate COE file when using MemoryEditor. This file can be used to define the data content of memory block (COE file). COE file: It is an input file in ASCII format. This file is used when a core needs to configure multiple data. For example, specify multiple coefficients for FIR filter, specify mask mode for correlator, and specify initialization value for memory module. XAW file: a binary file, one of a series of output files when using CoreGen to generate a Core, which stores the parameters set when using the "architecture Wizard" to generate the core. When re-customizing the core, the XAW file can be used as an input file to prompt the original settings. XCO file: one of a series of output files when using CoreGen to generate a Core, which stores the parameters required to generate the core. When re-customizing the core, the XCO file can be used as an input file to prompt the original settings. 3. Output files ASY file: a graphic symbol file used by ISE or third-party interface software to represent the core. coregen.log file: hence the name, it is the log file in the coregen process. EDN file: It is the EDIF implementation Netlist file of the Core, which is used to describe the implementation method of the Core. It is the input file for ISE implementation. padded.edn (omitted) flist.txt: A list of all output files. MIF file: Memory initialization file. It is a memory initialization file. This file is automatically generated when the HDL simulation flow is specified. This file can be used to support HDL functional simulation of certain modules. For example, the memory, FIR filter and bit correlator mentioned above. NDF file: This is an optional output file when generating a core with an NGC file. This file allows third-party synthesis tools to use the NGC file to derive resource utilization and timing information. NGC file: A binary Xilinx implementation netlist file. The logical implementation of some CoreGen IP is described by a top-level EDN file plus several NGC files. padded.edn (omitted) SYM file: Schematic symbol file. When using the ISE schematic editor, it is used to instantiate the Core's graphics. UCF file: User constraint file. This file is generated when the core is generated using the architecture wizard. The constraints in the file will be pasted into the UCF file of the ISE project V file: Verilog wrapper file, which is used to support Verilog functional simulation for the core. The V wrapper passes user-defined parameters to the general core simulation model file. If the V output file is named core_name_for.v, then the file supports formal verification. VEO file: Verilog template file. The components in this file can be used to instantiate a core. VHD file: This file has the same function as the V file, except that it is in VHDL format. VHO file: This file is the same as the VEO file, except that it is in VHDL format. XAW file: A binary file that contains the configuration information of the architecture wizard core. This file is generated by CoreGen when generating the Architecture wizard core. This file can also be used as input for CoreGen. XCO file: This file stores the project and Core parameters required to generate a specific core. The XCO file is automatically generated when a Core is created in the project directory. XSF file: A xilinx netlist format port list file. Menter Graphics calls this file when creating the symbol of the core.