Storage management of TI C2000 DSP chip

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Storage management of TI C2000 DSP chip [Copy link]

The performance of a DSP is affected by its ability to manage the memory subsystem. As mentioned earlier, the MAC and some other signal processing functions are the basic signal processing capabilities of DSP devices. Fast MAC execution requires reading one instruction word and two data words from memory in each instruction cycle. There are many ways to implement this reading, including multi-interface memory (allowing multiple accesses to memory in each instruction cycle), separate instruction and data memory ("Harvard" structure and its derivatives), and instruction cache (allowing instructions to be read from the cache instead of memory, thereby freeing up memory for data reading). Also pay attention to the size of the supported memory space. The main target market for many fixed-point DSPs is embedded application systems, where memory is generally small, so these DSP devices have small to medium on-chip memory (4K to 64K words) and a narrow external data bus. In addition, the address bus of most fixed-point DSPs is less than or equal to 16 bits, so the external memory space is limited. Some floating-point DSPs have very little or no on-chip memory, but a wide external data bus. For example, TI's TMS320C30 has only 6K on-chip memory, a 24-bit external bus, and a 13-bit external address bus. ADI's ADSP2-21060 has 4Mb of on-chip memory, which can be divided into program memory and data memory in a variety of ways. When choosing a DSP, you need to choose based on the specific application's requirements for storage space and external bus.