About MSP430 Timer A

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About MSP430 Timer A [Copy link]

The main functional modules of 16-bit TIMER_A include: . A counter that can continuously count up to a predetermined value and return to 0, or it can stop. . Software selectable clock source. . The selected clock source can be divided by 1, 2, 4 and 8. . 5 capture/compare registers. Each has an independent capture event, that is, 2 capture signals controlled by hardware and software. . 5 output modules, support pulse width modulation required. Timer operation: Mode control mode specific operation MC1 MC0 (TATCL register 4~5 bits) 0 0 Stop timer pause 0 1 Up-count timer counts up to the value equal to the compare register 0 1 0 Continuous timer counts up continuously 1 1 Up/down count timer counts up to the value equal to the compare register 0, and then counts down to 0 Input frequency division control bit (TACTL6~7) ID1 ID2 Frequency division description 0 0 PASS Input signal passes through the timer 0 1 /2 Input signal divided by 2 1 0 /4 Input signal divided by 8 Timer clock source: SSEL2 SSEL1 SSEL0 Input signal description 0 0 0 TACLK Use specific external pin signal 0 0 1 ACL Use auxiliary clock ACLK 0 1 0 MCLK Use system clock MCLK 0 1 1 INCLK See device description 1 XX ---- Reserved Capture mode: The setting of the mode bit CAPX in the control word CCTLX will select the capture mode. The capture mode is used for precise positioning of the time. It can be used in speed calculation or time measurement. If the selected pulse trigger edge occurs on the selected input pin, the value of the timer count will be copied to the capture register CCRX. After the capture is completed. The interrupt flag CCIFGX in the control word CCTLX is set;. If the general interrupt enable bit GIE and the corresponding interrupt flag bit CCIEX are set, an interrupt request is generated. Reset indicates that the capture data has been read before the next capture is completed. If the second capture data has been latched before the capture data is read, the overflow bit COVX in register CCTLX is set. Checking this bit can recover the program from the out-of-sync state. Software is required to reset COVX. CCRX_Int_hand ... ;Interrupt processing ... ... MOV &CCRX,RAM_Buffer BIT #COV,&CCTLX ; The impact of the BIT instruction on each flag bit: N is set when the highest bit is, Z is set when the result is 0, ;C is set when the result is non-zero; V is reset JNZ Overflow_Hand ;JNZ jumps when it is non-zero, handles overflow error, otherwise handles normally .... .... RETI Overflow_Hand BIC #COV,&CCTLX ;Reset the capture overflow flag and restore synchronization .... .... RETI When the timer is paused, the capture should be stopped. The order should be to stop the capture function first, then stop the timer count. When the capture function is restarted, the order should be to start the capture function first, then start the timer count. Compare mode: If CAPX in the control word CCTLX is reset, the compare mode is selected. At this time, all capture hardware stops working.If the timer count value is equal to the value in compare register X, then the interrupt flag CCIFX in the control word CCTLX is set. If GIE and CCIEX are set, an interrupt request is generated. The EQUX signal is output to the output unit OUTX. Depending on the selected output mode, the signal can be set, reset, or flip the output OUTX (if OUTMODX>0). When the timer value is greater than or equal to the value of CCR0, the EUQ0 signal is true; when the timer value is equal to the corresponding value of CCR1~CCR4, the EQU1~EQU4 signals are true. Output unit: The output unit supports PWM or DAC applications OUTMODX mode description 000 The data of the output mode OUTX bit is the OUTX signal 001 Set the comparison signal EQUX to set the OUTX signal 010 PWM flip/set comparison signal EQUX flips OUTX signal, EQU0 resets OUTX signal 011 PWM set/reset comparison signal EQUX sets OUTX signal, EQU0 resets OUTX signal 100 Flip comparison signal EQUX flips OUTX 101 Reset comparison signal EQUX resets OUTX 110 PWM flip/reset comparison signal EQUX flips OUTX signal, EQU0 sets OUTX signal 111 PWM reset/set comparison signal EQUX resets OUTX signal, EQU0 sets OUTX signal The output starts from the existing level regardless of the selected mode. 1. Up-counting mode: When the timer counts up to CCRX and counts from CCR0 to 0, the OUTX signal changes according to the selected output mode. 2. Continuous counting mode: When the timer counts to CCRX and counts to CCR0, the OUTX signal changes according to the selected output mode. 3. Up/down counting mode: When the timer counts up to CCRX and counts down to CCRX, the OUTX signal changes according to the selected output mode.