[LPC8N04 Review] 4. Detailed explanation of LPC8N04 chip NFC

北方

[LPC8N04 Review] 4. Detailed explanation of LPC8N04 chip NFC [Copy link]

1. The main features of the LPC8N04 chip NFC specification are - Compatible with ISO/IEC 14443 A 1-3 compatible - Compatible with Philips' proprietary MIFARE (Ultralight) technology, and NFC in the same frequency band 13.56MHz contactless identification technology - Direct user memory space read and write command access - Built-in 50 pF capacitor, compatible with standard NFC antenna RFID/NFC read and write based on MIFARE's 13.56MHz contactless identification technology. The RFID works internally at 6.78MHz, and the clock comes from the radio frequency signal, which is independent of the LPC8N04 clock. Among them, the RFID read and write fame can directly access the shared memory of the EEPROM, and this read and write command can be blocked when encrypted according to the MIFARE protocol. 2. Functional Description 2.1 The pins are connected to external pins through LA and LB, and a 50 pF capacitor is connected in parallel between LA and LB. 2.2 Memory Allocation The memory map table that the RF interface can access is as follows, Segment 0 is from 0x00 to 0x03, and the boundary between Segment 1 and Segment 2 is set here. For the READ command, 4 pages x 4 bytes will be read. Therefore, when reading 0x05E to 0x61, the first 4 bytes are the selected address, and the other 12 bytes are filled with 0x00. Reading the cache address (0x04 to 0x7F) returns 4 pages, so reading (0x80 to0x83) returns pages 3, 2 and 1, and the rest are filled with 0x00. For the WRITE command, the default is to write 1 page each time. COMP_WRITE sends 16 data bytes, but only the lowest 4 bytes are written to the address page. 2.3 Start communication When the NFC reader such as a mobile phone selects LPC8N04, the communication is started. The access to the shared memory is determined by the arbitration mechanism on the RF side or the APB bus. The interpretation of this communication command is performed by the firmware. 2.4 Register communication buffer capacity is 4k bit (128x4k bytes). The numbers seen from the RF side and the APB side are different, and need to be read from the table, such as the status register is 0x004 on the video side and 0x84 on the APB side. 2.5 Cache memory The cache address is 0x4005 8100 to 0x4005 82FC on the APB side and 0x04 to 0x83 on the RF side. The cache memory is used for the exchange of PHDC or NDEF information, and the data at startup is arbitrary. 3. As an NFC protocol, you can refer to relevant websites and standards.