The B channel of TMS320F28035 cannot output the correct waveform in the up-down mode of ePWM

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The B channel of TMS320F28035 cannot output the correct waveform in the up-down mode of ePWM [Copy link]

 I plan to use the 28035 ePWM module to output center-aligned waveforms on both AB paths. It looks like the following The code directly refers to TI’s TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM) Module document, document number SPRUGE9E;

1. void InitEPwm1(void) { EPwm1Regs.TBPRD = 600; // Period = 2′600 TBCLK counts EPwm1Regs.CMPA.half.CMPA = 400; // Compare A = 400 TBCLK counts EPwm1Regs.CMPB = 500; // Compare B = 500 TBCLK counts EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero EPwm1Regs.TBCTR = 0; // clear TB counter EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetric EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Phase loading disabled EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLKOUT EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR = Zero EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR = Zero EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; EPwm1Regs.AQCTLB.bit.CBU = AQ_SET; EPwm1Regs.AQCTLB.bit.CBD = AQ_CLEAR; }

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According to the parameters of this code, the PWM period should be 50KHz, no problem. The positive duty cycle of channel A should be 33.3%. There is an inverter in my circuit, and the measured waveform has a positive duty cycle of 62%. Considering the measurement error caused by waveform distortion, this waveform can be considered correct. Changing the value of CMPA will change the waveform duty cycle, and the error is basically fixed. Let's take a look at the waveform of channel B. The positive duty cycle should be (600-500)*2/1200=16.6%, and it is 83.4% after the reverse. The actual measured duty cycle is 41%, that is, 500/1200, which means that the code is actually executed in the increasing stage, and it is a low level when it is 0-500. After matching CMB, it becomes a high level. In the decreasing stage, the match is not completed, but it can be reduced to 0 and then become low. I can't see anything wrong with the code. And it is the official reference code. Are there any friends who have used this module who can give me some advice. Thank you