EMC recommendations to consider at the beginning of single-chip system design, good summary

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EMC recommendations to consider at the beginning of single-chip system design, good summary [Copy link]

This article mainly refers to "MICROCONTROLLER DESIGN GUIDELINES FOR ELECTROMAGNETIC COMPATIBILITY". Although this article was written many years ago, it has a lot of practical reference significance. In addition, other IC manufacturers also have a lot of reference documents. If you are interested, you can refer to them. Off topic, this topic is mainly to analyze the main interference sources and sensitive devices inside the module, and slowly understand the EMC design of the module through the design of these main things. However, it is inevitable that there are some superficial suspicions. With more accumulation, it may be easy to consider the problems in the early stage of circuit design in the future. 1. Operating frequency of MCU 1.1. The design of MCU should choose a lower operating frequency according to customer needs First, let me introduce the advantages of doing so: using low crystal oscillator and bus frequency allows us to choose a smaller MCU to meet the timing requirements, so that the operating current of the MCU can become lower, and the most important thing is that the current peak from VDD to VSS will be smaller. Of course, we need to make a compromise here, because the customer's requirements may be compatible and platform-based (the current development trend of automotive electronics is platform-based), choosing a higher operating frequency can be compatible with more platforms, and it is also convenient for future upgrades and expansions, so we should choose a lower acceptable operating frequency. 2. Appropriate output drive capability Given the load specification, rise and fall time, choosing the appropriate output rise time and minimizing the peak current of the output and internal driver are one of the most important design considerations for reducing EMI. Unmatched drive capability or failure to control the output voltage change rate may result in impedance mismatch, faster switching edges, overshoot and undershoot of the output signal, or power and ground bounce noise. 2.1. When designing the output driver of the microcontroller, first determine the module's required load, rise and fall time, output current and other parameters. Based on the above information, drive capability and control voltage slew rate. Only in this way can we get a device that meets module requirements and meets EMC requirements. Drivers with higher capacity than the load actually needs to charge will produce higher edge rates, which has two disadvantages: 1. The harmonic content of the signal increases. 2. Together with the load capacitance and parasitic internal bonding lines, IC package, and PCB inductance, it will cause overshoot and undershoot of the signal. The selection of the appropriate di/dt switching characteristics can be achieved by carefully selecting the size of the drive capacity and controlling the voltage slew rate. The best choice is to use a constant voltage slew rate output buffer that is independent of the load. The voltage slew rate of the same pre-driver output can be reduced (i.e., the rise and fall times can be increased), but the corresponding propagation delay will increase and we need to control the total switching time). 2.2. Use the drive capability of the programmable output port of the microcontroller to meet the actual load requirements of the module. The simplest driver of the programmable output port is a pair of drivers in parallel. Their MOS Rdson is different and the output current capacity is also different. We can choose different modes during testing and actual use. In fact, the current microcontrollers generally have at least two modes to choose from, and some even have three (strong, medium, weak) 2.3. When the timing constraints have enough margin, slow down the edge of the internal clock drive by reducing the output capacity. To reduce the peak current and di/dt of the synchronous switch, an important consideration is to reduce the internal clock drive capacity (in fact, it is the amplification factor, and the through current is greatly related to it). Reducing the current on the clock edge will significantly improve EMI. Of course, the disadvantage of this is that the average current of the microcontroller may increase due to the longer turn-on time of the clock and the load. A compromise needs to be made between fast edges and relatively high peak currents, and current pulses with longer edges and slower edges. 2.4. The internal drive (inverter) of the crystal oscillator should not exceed the actual demand. This issue has actually been discussed before. When the gain is too large, it will bring greater interference. 3. Design drivers with minimum through-current 3.1. Clock, bus and output driver should minimize traditional current Through-current [overlap current, short-circuit current] is the current from the power supply to the ground when the PMOS and NMOS are turned on at the same time during the switching process of the microcontroller. The through-current directly affects EMI and power consumption. This content is actually inside the microcontroller, clock, bus and output driver. The way to eliminate or reduce the through-current is to try to turn off one FET first and then turn on another FET. When the current is large, additional pre-drive circuits or voltage slew rates are required. 4. Clock Generation and Distribution 4.1 As far as the microcontroller is concerned, we would rather distribute the clock to each part (the smallest high-frequency clock possible), of course we need to manage the clock offset. This is much better than using a clock buffer with a large gain to drive the clock of the entire IC Synchronous CMOS design generates a large peak current at the clock edge. The use of the clock tree structure (under the conditions that the system time allows) will reduce the synchronous switching current compared to the main clock driver and clock distribution line. [The inherent delay time in the clock tree structure makes the switch separate at different times] 4.2. Use power management technology. Put the clock source as close as possible to the required IC if the clock needs to be distributed within a module. When the clock is not needed, turn off the clock source. [Clock switching is usually required in sleep mode] 4.3. Use non-overlapping clocks whenever possible, as system constraints permit. Non-overlapping clocks are clocks without synchronous edges. From a system perspective, non-overlapping clock edges help eliminate race conditions and metastability. From an EMC perspective, adding transition time between clock edges reduces peak current and peak amplitude of harmonics. The average current will remain roughly the same over time, but the amplitude and spectral shape will change. If the transitions between clocks are close but not synchronous (assuming the edge speed is much faster than the clock period), the current waveform will become flatter and the duration will become longer. As the transition time increases, the current waveform will be separated into several pulses for each edge. The lower pulse amplitude correspondingly reduces the spectral amplitude of the harmonics, and the current pulse edges are likely to remain roughly the same (maintaining the pulse bandwidth). Ideally, the non-overlapping duty cycle in a two-phase system is 33%, maximizing the time between clock edges. However, it is not possible to use this approach in practical applications. Some compromises must be made. The actual system does not allow such a large span of clock edges. 4.4. Keep the clock circuit as far away from the I/O logic circuit as possible to reduce the possibility of common-mode radiation problems. The clock signal needs to be away from the I/O logic or parallel leads. The clock transient edge can couple to the I/O logic and generate voltage noise. 4.5. Move the input pin synchronizer away from the microcontroller pin area and into the core module of the microcontroller. This method can reduce the size of the required clock driver. Moving the synchronizer closer to the clock source can reduce the length of the clock signal line. The capacitive load on the clock driver depends in part on the parasitic capacitance of the leads, and the clock driver charging load will become smaller.