Application skills/Using 68HC908GP32 single-chip microcomputer to realize EPP enhanced parallel port interface technology

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Application skills/Using 68HC908GP32 single-chip microcomputer to realize EPP enhanced parallel port interface technology [Copy link]

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Abstract : This paper introduces several operation modes of computer parallel port, and gives several schemes for realizing EPP interface design; it focuses on the implementation of EPP interface design using Motorola's 68HC908GP32 single-chip microcomputer, and gives a design scheme for a data acquisition system realized by GP32 single-chip microcomputer.
	Keywords : EPP Enhanced Parallel Port MCU 68HC908GP32
	1. Overview of computer parallel port operation mode
	1.SPP mode
	SPP (Standard Parallel Port) mode is the standard parallel port mode, which is designed for printing output. Data is output from the computer in one direction, and data cannot be input using the data line. Data input can only be done using the status line. There are only 5 parallel port status lines, so each byte must be input twice and then assembled into a complete byte. SPP mode has a low speed and low hardware requirements. It is suitable for low-speed applications such as printers, software dogs, etc.
	2.PS/2 mode
	After IBM introduced the PS/2 design, it began to support bidirectional data transmission of the parallel port. The PS/2 mode is compatible with the SPP mode. It does not change the signal definition of the standard parallel port, nor does it change the pin definition of the parallel port connector. Instead, it uses a direction control bit to set the data direction of the parallel port: if it is set to output, the PS/2 mode is exactly the same as the SPP mode; if it is set to input, one byte of data can be read from the parallel port data line at a time. At the same time, the bus control function of the PS/2 mode increases the speed of the parallel port.
	Whether in SPP mode or PS/2 mode, the data communication reliability is not high. The reason is that the I/O speed of the parallel port itself is not high (only 100-400KB/s). On the other hand, each data transmission must be exchanged through software data through I/O operations. Usually, a data transmission of an interlocked data exchange requires at least 5 I/O operations to ensure the integrity of the sequence. These two factors make SPP mode and PS/2 mode only applicable to low-speed applications.
	3.EPP mode
	EPP (Enhanced Parallel Port) mode supports bidirectional data exchange between the parallel port and peripherals at a speed of 1-2MB/s. The enhanced parallel port ensures the speed and accuracy of data transmission through a precise logical interface and clearly defined electrical parameters.
	4.ECP mode
	ECP (Extended Capabilities Port) mode, that is, extended functions and modes, has higher performance. ECP mode has a 16-byte FIFO and supports DMA function. It reduces the burden on the computer CPU without reducing system performance and improves the overall performance of the application system. More importantly, the ECP mode incorporates several other parallel port modes into the definition of the ECP mode. The ECP mode defines the ECR extended control register, which can set the parallel port operation mode to SPP, PS/2, EPP or ECP, thus forming a complete parallel port system.
	SPP mode, PS/2 mode and EPP mode are all master-slave structures, and the two parties of data transmission are in an unequal relationship. Data transmission can only be initiated by the computer, and the peripheral cannot initiate data transmission. If the peripheral wants to perform data transmission, it can only request an interrupt from the computer, and then the computer will initiate the data transmission. ECP mode is not a master-slave structure, and both parties of data transmission can initiate data transmission. ECP mode can be used for interconnection between computers, while EPP mode cannot.
	Although the performance of ECP parallel port mode is higher than that of EPP, it is not easy to implement. Most designers use EPP mode to design their own application systems. EPP mode is simpler, more flexible and reliable than ECP mode, and has been more practically applied in the industry.
	2. Implementation of EPP enhanced parallel port
	1.EPP gain parallel port timing
	The EPP protocol defines four parallel port cycles: data write cycle, data read cycle, address write cycle and address read cycle. The data cycle is used to transfer data between the computer and the peripherals; the address cycle is used to transfer auxiliary information such as address, channel, command, control and status.
	Figure 1 is a timing diagram for EPP data writing. The nIOW signal in the figure is not actually generated when EPP data is written. It just means that all operations occur in one I/O cycle. At t1, the computer detects the nWAIT signal. If nWAIT is low, it means that the peripheral is ready and can start an EPP cycle. At t2, the computer sets the nWRITE signal to low, indicating that it is a write cycle, and drives the data line at the same time. At t3, the computer sets the nDataStrobe signal to low, indicating that it is a data cycle. After the peripheral detects that nDataStrobe is low, it reads the data and performs corresponding data processing. At t4, nWAIT is set to high, indicating that the data has been read and the computer can end the EPP cycle. At t5 and t6, the computer sets nDataStrobe and nWRITE to high. In this way, a complete EPP data write cycle is completed. If the nDataStrobe signal in Figure 1 is replaced with the nAddStrobe signal, it is an EPP address write cycle.
	Figure 2 shows the EPP address read cycle. It is similar to the EPP write cycle, except that the data line is driven by the peripheral.
	The EPP timing also includes initialization, interrupt application, etc. You can refer to reference 1 for detailed timing diagrams and timing descriptions.
	2. EPP gain parallel port logic interface
	The EPP enhanced parallel port mode uses the same base address as the standard parallel port mode and defines 8 I/O addresses. Base address + 0 is the SPP data port, base address + 1 is the SPP status port, and base address + 2 is the SPP control port. These three ports are actually the data, status, and control ports in the SPP mode, thus ensuring the software and hardware compatibility of the EPP mode and the SPP mode.
	The base address + 3 is the EPP address port. Writing data to this I/O port will generate a chained EPP address write cycle, and reading data from this I/O port will generate a chained EPP address read cycle. In different EPP application systems, the EPP address port can be designed as device selection, channel selection, control register, status information, etc. according to actual needs, providing great flexibility to the EPP application system.
	Base address +4 is the EPP data port. Writing data to this I/O port will generate a chained EPP data write cycle, and reading data from this I/O port will generate a chained EPP data read cycle. Base address +5 to +7 together with base address +4 provide the double-word operation capability of the EPP data port. EPP allows the host to write a 32-bit double word in one clock cycle, and the EPP circuit then splits the 32-bit double word into 4 bytes and sends them out from the EPP data port in sequence. Data can also be transmitted in 16-bit word mode.
	3. EPP enhanced parallel port peripheral hardware implementation solution
	The speed of EPP enhanced parallel port can reach 1-2MB/s, which puts forward a high requirement for the interface design of peripherals. If the peripheral response is too slow, the overall performance of the system will be greatly reduced. The EPP interface design is the key to the overall performance of the entire EPP application system.
	(1) Gate circuit implementation
	This implementation can realize the basic interface, but it cannot make specific processing for the address cycle. The biggest disadvantage of the gate circuit implementation is the lack of basic flexibility and no confidentiality measures. Any change in the design requires the redesign of the entire interface system. Therefore, this implementation is not recommended.
	(2) Implementation of programmable logic devices
	User programmable logic devices such as FPGA and CPLD can realize the interface design of EPP enhanced parallel port. This implementation can reach the speed limit of parallel port and provide great flexibility. FPGA has large capacity, low power consumption and rich register resources, and can integrate other complex interfaces and controls of EPP application system into one chip. The disadvantage is that FPGA needs to be configured before each use, and FPGA has poor anti-interference ability and is easy to lose configuration information in harsh environment. CPLD has small capacity, high power consumption and scarce register resources, and can realize EPP interface and some less complex interfaces and control functions. CPLD uses EEPROM or FLASH to save configuration information, which will not be lost when power is off. Programmable logic devices are the preferred implementation solution for EPP application system.
	(3) DSP implementation
	DSP has a short instruction cycle and a fast CPU, and can also be used to implement the interface design of the EPP enhanced parallel port. However, DSP itself is used for calculations, and the operation efficiency of the interface control instructions is not high, and the interface speed is not as fast as the programmable logic device implementation solution. If the EPP application system requires relatively strong computing power, using DSP to implement the interface and computing functions of the entire application system is a more appropriate choice.
	(4) MCU implementation
	It seems incredible to use a single-chip microcomputer to implement the EPP interface, because the speed of the single-chip microcomputer is relatively slow, and the execution of instructions is serial. It cannot divide a large task into several independent small tasks for parallel processing like CPLD or FPGA. The author has always used programmable logic devices to implement the EPP interface design, and thought that it is impossible to implement the EPP interface design with a single-chip microcomputer. After learning about the excellent overclocking performance of Motorola's 68HC908GP32 (GP32 for short) single-chip microcomputer, the GP32 single-chip microcomputer was used to implement the EPP interface design. Practice has shown that the GP32 single-chip microcomputer can complete the EPP interface task very well, and its performance can fully meet the requirements of both computers and peripherals. The rich external and efficient I/O instruction system of the GP32 single-chip microcomputer makes up for the lack of slow speed. If the overall function of an EPP application system is considered, using a single-chip microcomputer to implement the interface and control functions is the most cost-effective implementation solution.
	3. Using 68HC908GP32 MCU to implement EPP interface design
	1.68HC908GP32 MCU Function Overview
	68HC908GP32 is a 68HC08 series microcontroller launched by Motorola in 1999. GP32 uses 68HC08CPU, and its performance is 5 to 10 times that of 68HC05CPU. GP32 has 32KB FLASH flash memory, online programming capability and super confidentiality function; 512 bytes of RAM, enhanced serial communication port SCI, serial peripheral interface SPI; two 16-bit dual-channel timer interfaces, each channel can be selected as input capture, output comparison or PWM, and its timing clock can be 1, 2, 4, 8, 16, 32 and 64 divisions of the internal bus; there are 8-channel 8-bit A/D converters, 8-bit keyboard wake-up port, and 29 general I/O pins. System protection features are: computer working properly (COP) reset, low voltage detection reset, illegal instruction detection reset and illegal address detection reset.
	2. GP32 clock generation module
	GP32 has a clock generation module, which can generate an operating frequency of up to 19.5MHz using a 32kHz crystal oscillator and an on-chip PLL (phase-locked loop) circuit. General single-chip microcomputers cannot be overclocked, otherwise the chip will not operate normally due to factors such as code reading errors, code running errors, and chip heating, and will frequently crash, or even burn the chip. The CPU of GP32 normally operates at a frequency of 8MHz, but it can still run stably at 2.4 times the rated frequency. The author conducted an experiment in which GP32 operated at 19.5MHz and ran stably for 90 hours in a laboratory environment, and ran stably for 90 minutes near the brushes of a DC generator in a power system dynamic simulation laboratory. There was no unexpected crash during the operation. The experiment shows that the GP32 single-chip microcomputer can be overclocked for a long time.
	3. Using GP32 MCU to implement EPP enhanced parallel port interface design
	The EPP enhanced parallel port defines 8 data lines, 2 status lines and 3 control lines. The bidirectional I/O lines of GP32 can be directly connected to the signal lines of EPP. The GP32 microcontroller has sufficient driving capability to drive the parallel port signals.
	Software design is the key to implementing the EPP interface design with the GP32 microcontroller. In order to ensure the communication speed, the instructions of the GP32 microcontroller must be optimized and those with fast execution speed must be selected; at the same time, a reasonable data flow control method must be adopted to ensure both the speed of communication and the correctness of the communication data. For example, large batches of data are transmitted in the form of data packets, and data is processed in units of data packets.
	At an operating frequency of 19.5MHz, the EPP enhanced parallel port implemented by GP32 can reach a communication speed of 400KB/s. If the operating frequency of GP32 is reduced, the communication speed will be reduced proportionally, but the minimum cannot be lower than 100B/s, otherwise the communication will fail due to the slow response of the peripheral.
	4. Data acquisition board implemented with GP32 microcontroller
	The GP32 microcontroller has 8-channel 8-bit AD converters, which can be used in some applications that require low sampling speed and low resolution. The author designed a data acquisition system using the GP32 microcontroller, and the circuit diagram is shown in Figure 3. U1 is the GP32 microcontroller, JAD is the analog signal input interface, PARAPORT is the parallel port, C1, C2, C3, X1, and RB are RS, which together constitute the GP32 microcontroller phase-locked loop circuit.
	The A/D conversion channel and start conditions can be set through the computer, and A/D sampling can be started or stopped. GP32 has 512 bytes of on-chip RAM, of which 384 bytes are set as the A/D conversion buffer, and the remaining RAM is used as a stack and variables. If the A/D conversion buffer is full of 256 bytes, the GP32 microcontroller sends an interrupt to the computer, and the computer reads the A/D conversion data using the EPP parallel port protocol.
	A hardware driver in the computer handles the hardware interrupt of the parallel port. The driver reads the result of A/D conversion through the EPP parallel port in the parallel port interrupt service program, and sends a message to the RING3 application to notify the application to read the data. The application further analyzes and processes the data, such as graphic display, data file access, etc.