Application Tips/Practical Step-by-Step PWM Output Using 89C51 and 8254-2

rain

Application Tips/Practical Step-by-Step PWM Output Using 89C51 and 8254-2 [Copy link]

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	Abstract : This paper introduces a new PWM output method. It uses 89C51 as the main control part and 8254-2 programmable timer/counter to achieve 1Hz~3kHz step-by-step PWM output. It has the advantages of high resolution, fast response speed and less CPU time occupation.
	Keywords : 8254-2 89C51 pulse width modulation (PWM) resolution
	introduction
	Pulse width modulation (PWM) technology was originally used for signal modulation in radio technology, and later it was well applied in motor speed regulation. In this design, the output PWM is required to increase step by step from 1Hz to 3kHz, with a single step of 1Hz. Since the maximum clock of 89C51 can be 24MHz, the single instruction cycle is 0.5μs, and the counting frequency is ×10 6Hz. When outputting 2999Hz and 3000Hz, if the internal counter of 89C51 is used to count, it is impossible to distinguish. Because the counting frequency is 2MHz, the single instruction cycle is 0.5μs, and when outputting 2999Hz, the count should be 666.889; when outputting 3000Hz, the count should be 666.887. Therefore, in this design, the external timer/counter 8254-2 is used. Because the maximum counting frequency of 8254-2 can reach 10MHz, it can meet the requirements of the above design. In addition, the working mode 3 of 8254-2 can output square waves. When the timer/counter 8254-2 works in mode 3, the output is high for half of the time and low for the other half of the time during the counting process. Therefore, if the count value is N, its output can output a high level in the first N/2 and a low level in the last N/2. There is no need to use software to control the conversion of high and low levels. However, the counting range of 8254-2 is limited to a certain extent. When binary counting is used, the range is 0000 to 9999, and the maximum count is 10,000. In addition, in order to meet the resolution requirements, the time occupied by the program instructions must also be considered, especially when outputting high frequencies, resolution is particularly important.
	1 Hardware Design
	1.1 Introduction to 8254 Programmable Timer/Counter[1]
	Intel's 8254 is an improved version of the 8253, and its operation mode and pins are exactly the same as those of the 8253. Its improvements are mainly reflected in two aspects: ① The counting frequency of the 8254 is higher, from DC to 6MHz; the 8254-2 can be as high as 10MHz. ② The 8254 has more than 1 read-back command (write to the controller's register), and its format is shown in Figure 1.
	This command can latch the counters of all three channels (8253 needs to write three commands to latch the count values of all three channels). In addition, each counter in 8254 has a status word that can be latched by the read-back command and then read by the CPU. The format of the status word is shown in Figure 2. Among them, D5~D0 are the corresponding parts of the control word written to this channel. D7 reflects the output pin of the counter. When the output (OUT) is high, D7=1; when the output is low, D7=0. D6 reflects whether the count value in the time constant register has been written into the count unit. When the control word and count value are written to the channel, D6 in the status byte=1; only when the count value is written into the count unit, D6=0.
	This design chooses mode 3 of 8254-2. Mode 3 is a square wave rate generator. In this mode, when the CPU sets the control word, the output will be high, and the counting will start automatically after the count value is written, and the output remains high; when the count reaches half of the count value, the output becomes low, until the count reaches 0, the output becomes high again, and the counting starts again. If a new count value is written during the counting period, it does not affect the current counting process. However, if a GATE pulse is received before the end of the square wave half cycle and after the new count value is written, the counter will load the new count value at the next CLK pulse and start counting at this count value. Otherwise, the new count value will be loaded into the counter at the end of the current half cycle.
	1.2 Hardware Design of PWM Output
	This design uses the programmable timer/counter 8254-2, whose maximum counting frequency can reach 10MHz; it makes full use of the three timers/counters of 8254-2, adopts frequency division output, and does not require external signal source input, simplifying the hardware circuit; through software processing, it can achieve continuous (1Hz~3kHz) PWM wave output. In this design, the PWM wave to be output is divided into 3 segments, which are output by the three timers/counters in 8254-2, and the gate control is controlled by P2.2, P2.3, and P2.4 respectively. When the output is 1 to 20 Hz, timer 0 is used, the counting frequency is 10 4 Hz, the maximum count is 10 4, and the minimum count is 500, which meets the requirements. When the output is 21 to 200 Hz, timer 1 is used, the counting frequency is 10 5 Hz, the maximum count is 4762, and the minimum count is 500. When the output is 201 Hz to 3 kHz, timer 2 is used, the counting frequency is 10 7 Hz, the maximum count is 49 751, which meets the range of binary counting, and the minimum count is 3333. These count values can be sent to the data input terminal of 8254-2 by the single-chip microcomputer 89C51 [2], and these count values are obtained by division operation, and the quotient is obtained by division operation. The quotient minus the time occupied by the program instruction is the required count value. The outputs of the three timers of 8254-2 are used as the input of the CD4046 phase-locked loop through an OR gate, and at the same time enter the INT1 port of 89C51 through a NOT gate to apply for a falling edge interrupt; the CD4046 phase-locked loop outputs the required PWM.
	In order to prevent the program from entering an infinite loop, an external hardware watchdog timer IMP813L[3] is added. Its internal watchdog timer monitors the operation of UP/UC. If its operation is not detected within 1.6s, the internal timer will put the watchdog output WDO in a low state. WDO will remain low until the operation of UP/UC is detected at WDI. Connecting WR and WDO can cause the watchdog timeout to generate a reset.
	The specific hardware circuit is shown in Figure 3.
	2 Software Design
	The software mainly consists of three parts: main program, keyboard scanning program, and interrupt processing program. The main program flow is shown in Figure 4. The main address allocation is listed in Table 1.
	(1) Interrupt handling process
	When 89C51 detects INT1 interrupt, it enters the interrupt processing program, first checks whether the content in 30H and 31H is greater than 20; if not, gate is P2.2, selects 8254-2, selects counter 0, mode 3, 16-bit binary counting, sends the count value calculated last time to 8254-2, sends 10 4 to 32H and 33H as the dividend in the division operation, and the content of 30H and 31H is used as the divisor in the division operation, calls the division operation subroutine to send the quotient to 32H and 33H, and the remainder is placed in 35H and 36H. Compare whether the remainder is greater than half of the divisor. If it is greater than half of the divisor, add 1 to the quotient, otherwise the quotient remains unchanged and is placed in 32H and 33H. Assume that the time occupied by the program instruction is X/200 (where X is the number of single instruction cycles in the interrupt program), subtract X/200 from the contents of 32H and 33H, which is the count value to be sent to 8254-2 next time, and put it in 35H and 36H, and return to the interrupt; if it is greater than 20, the gate is P2.3, 8254-2 is selected, counter 1 and mode 3 are selected, and the count value required this time calculated last time is sent to 8254-2, 10 5 is sent to 32H, 33H, and 34H as the dividend in the division operation, and the contents of 30H and 31H are used as the divisor in the division operation, and the division operation subroutine is called, and the quotient is sent to 32H and 33H, and the remainder is placed in 35H and 36H. Compare whether the remainder is greater than half of the divisor. If it is greater than half of the division, the quotient is increased by 1, otherwise the quotient remains unchanged. Assume that the time occupied by the program instruction is X/20, subtract X/20 from the content in 32H and 33H to get the count value to be sent to 8254-2 next time, put it in 35H and 36H, and return to the interrupt. If it is greater than 200, the gate is P2.4, 8254-2 is selected, counter 2, mode 3, binary counting are selected, and the count value required this time calculated last time is sent to 8254-2. 10 7 is sent to 32H, 33H, and 34H as the dividend in the division operation, and the content in 30H and 31H is used as the divisor in the division operation. The division operation subroutine is called, and the quotient is sent to 32H and 33H, and the remainder is placed in 35H and 36H. Compare whether the remainder is greater than half of the divisor. If it is greater than half of the divisor, add 1 to the quotient, otherwise the quotient is not entered into 32H and 33H. Assuming that the time occupied by the program instruction is X*5, subtract 5X from the contents in 32H and 33H, which is the count value to be sent to 8254-2 next time, and put it in 35H and 36H, and return the interrupt.
	(2) Setting up software traps
	When the program enters the non-program area, as long as the interception measures are set in the non-program area, the program enters the trap, and then the program is forced to return to the initial state. For example, the byte code corresponding to the CPU's RST instruction is 0FFH. If the unused program storage area is pre-written with 0FFH, when the program "flies" to the area to execute the code due to interference, it is equivalent to executing a RST instruction, thereby achieving the purpose of system reset.
	Conclusion
	Using 89C51 to control PWM segmentation, 8254-2 step-by-step output 1Hz~3kHz PWM, the resolution can be improved by software programming. In some special occasions, the timer or analog circuit inside the microcontroller cannot accurately output 1Hz~3kHz, and the single-step PWM waveform is 1Hz. This design shows its obvious superiority, and it occupies a short CPU time. This design has a simple structure, low cost, good reliability, and strong anti-interference ability, and can be used in control and measurement.

lorant

I feel a bit dizzy.

rain

No, this one isn't very long.

w451140607

Moderator, I would like to ask, if you use 82c54_2 and cd4046, how to achieve frequency increase, for example, the output of cd4046 is connected to the clk signal input of counter 0, D0-D7 controls the square wave frequency of timer 0 you selected, and then connects to pin 3 of cd4046 (comparison signal input), and then gets the signal at this time from cd4046, I can't find the pattern, can you please explain it to me