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How to adjust the duty cycle of C2000 [Copy link]

Dear seniors are learning how to use DSP In this example program Example_2806xEPwmUpDownAQ C2000 How to adjust the duty cycle?? I went to adjust the CMPA, but the duty cycle is still only 50%??How to adjust the duty cycle to 95%??[/ color] /////////////////////////////////////////////////// ///////////////////////////////////////////////////// ////////////////// __interrupt void epwm3_isr(void) { // Update the CMPA and CMPB values // update_compare(&epwm3_info); // Clear INT flag for this timer EPwm3Regs.ETCLR .bit.INT = 1; // Acknowledge this interrupt to receive more interrupts from group 3 PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; } #define EPWM3_TIMER_TBPRD 2000 // Period register 2000 #define EPWM3_MAX_CMPA 1800 #define EPWM3_MIN_CMPA 200 #define EPWM3_MAX_CMPB 1950 # EPWM3_MIN_CMPB 50 void InitEPwm3Example(void) { // Setup TBCLK EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up/down EPwm3Regs.TBPRD = EPWM3_TIMER_TBPRD; // Set timer period EPwm3Regs.TBCTL.bit.PHSEN = define TB_DISABLE; // Disable phase loading EPwm3Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 EPwm3Regs.TBCTR = 0x0000; // Clear counter EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT EPwm3Regs.TBCTL. bit.CLKDIV = 7; //TB_DIV1; // Setup shadow register load on ZERO EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // Set Compare values EPwm3Regs.CMPA.half.CMPA = EPWM3_MIN_CMPA; // Set compare A value EPwm3Regs.CMPB = EPWM3_MAX_CMPB; // Set Compare B value // Set Actions EPwm3Regs.AQCTLA.bit .PRD = AQ_SET; // Set PWM3A on period EPwm3Regs.AQCTLA.bit.CBD = AQ_CLEAR; // Clear PWM3A on event B, down count EPwm3Regs.AQCTLB.bit.PRD = AQ_CLEAR; // Clear PWM3A on period EPwm3Regs.AQCTLB .bit.CAU = AQ_SET; // Set PWM3A on event A, up count // Interrupt where we will change the Compare Values EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event EPwm3Regs.ETSEL.bit. INTEN = 1; // Enable INT EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event // Information this example uses to keep track // of the direction the CMPA/CMPB values are // moving, the min and max allowed values and // a pointer to the correct ePWM registers epwm3_info.EPwm_CMPA_Direction = EPWM_CMP_UP; // Start by increasing CMPA & epwm3_info.EPwm_CMPB_Direction = EPWM_CMP_DOWN; // decreasing CMPB epwm3_info.EPwmTimerIntCount = 0; // Zero the interrupt counter epwm3_info.EPwmRegHandle = &EPwm3Regs; // Set the pointer to the ePWM module epwm3_info.EPwmMaxCMPA = EPWM3_MAX_CMPA; // Setup min/max CMPA/CMPB values epwm3_info.EPwmMinCMPA = EPWM3_MIN_CMPA; epwm3_info.EPwmMaxCMPB = EPWM3_MAX_CMPB; epwm3_info.EPwmMinCMPB = EPWM3_MIN_CMPB; } void update_compare(EPWM_INFO *epwm_info) { // Every 10'th interrupt, change the CMPA/CMPB values if(epwm_info->EPwmTimerIntCount == 1) { epwm_info->EPwmTimerIntCount = 0; // If we were increasing CMPA, check to see if // we reached the max value. If not, increase CMPA // else, change directions and decrease CMPA if(epwm_info->EPwm_CMPA_Direction == EPWM_CMP_UP ) { if(epwm_info->EPwmRegHandle->CMPA.half.CMPA < epwm_info->EPwmMaxCMPA) { epwm_info->EPwmRegHandle->CMPA.half.CMPA++; } else { epwm_info->EPwm_CMPA_Direction = EPWM_CMP_DOWN; epwm_info->EPwmRegHandle-> CMPA.half.CMPA--; } } // If we were decreasing CMPA, check to see if // we reached the min value. If not, decrease CMPA // else, change directions and increase CMPA else { if(epwm_info- >EPwmRegHandle->CMPA.half.CMPA == epwm_info->EPwmMinCMPA) { epwm_info->EPwm_CMPA_Direction = EPWM_CMP_UP; epwm_info->EPwmRegHandle->CMPA.half.CMPA++; } else { epwm_info->EPwmRegHandle->CMPA.half.CMPA --; } } // If we were increasing CMPB, check to see if // we reached the max value. If not, increase CMPB // else, change directions and decrease CMPB if(epwm_info->EPwm_CMPB_Direction == EPWM_CMP_UP) { if(epwm_info->EPwmRegHandle->CMPB < epwm_info->EPwmMaxCMPB) { epwm_info->EPwmRegHandle->CMPB++; } else { epwm_info->EPwm_CMPB_Direction = EPWM_CMP_DOWN; epwm_info->EPwmRegHandle->CMPB--; } } // If we were decreasing CMPB, check to see if // we reached the min value. If not, decrease CMPB // else, change directions and increase CMPB else { if(epwm_info->EPwmRegHandle->CMPB == epwm_info->EPwmMinCMPB) { epwm_info ->EPwm_CMPB_Direction = EPWM_CMP_UP; epwm_info->EPwmRegHandle->CMPB++; } else { epwm_info->EPwmRegHandle->CMPB--; } } } else { epwm_info->EPwmTimerIntCount++; } return; }change directions and decrease CMPA if(epwm_info->EPwm_CMPA_Direction == EPWM_CMP_UP) { if(epwm_info->EPwmRegHandle->CMPA.half.CMPA < epwm_info->EPwmMaxCMPA) { epwm_info->EPwmRegHandle->CMPA.half.CMPA++; } else { epwm_info->EPwm_CMPA_Direction = EPWM_CMP_DOWN; epwm_info->EPwmRegHandle->CMPA.half.CMPA--; } } // If we were decreasing CMPA, check to see if // we reached the min value. If not, decrease CMPA / / else, change directions and increase CMPA else { if(epwm_info->EPwmRegHandle->CMPA.half.CMPA == epwm_info->EPwmMinCMPA) { epwm_info->EPwm_CMPA_Direction = EPWM_CMP_UP; epwm_info->EPwmRegHandle->CMPA.half.CMPA++; } else { epwm_info->EPwmRegHandle->CMPA.half.CMPA--; } } // If we were increasing CMPB, check to see if // we reached the max value. If not, increase CMPB // else, change directions and decrease CMPB if(epwm_info->EPwm_CMPB_Direction == EPWM_CMP_UP) { if(epwm_info->EPwmRegHandle->CMPB < epwm_info->EPwmMaxCMPB) { epwm_info->EPwmRegHandle->CMPB++; } else { epwm_info->EPwm_CMPB_Direction = EPWM_CMP_DOWN; epwm_info- >EPwmRegHandle->CMPB--; } } // If we were decreasing CMPB, check to see if // we reached the min value. If not, decrease CMPB // else, change directions and increase CMPB else { if(epwm_info- >EPwmRegHandle->CMPB == epwm_info->EPwmMinCMPB) { epwm_info->EPwm_CMPB_Direction = EPWM_CMP_UP; epwm_info->EPwmRegHandle->CMPB++; } else { epwm_info->EPwmRegHandle->CMPB--; } } } else { epwm_info->EPwmTime rIntCount++ ; } return; }change directions and decrease CMPA if(epwm_info->EPwm_CMPA_Direction == EPWM_CMP_UP) { if(epwm_info->EPwmRegHandle->CMPA.half.CMPA < epwm_info->EPwmMaxCMPA) { epwm_info->EPwmRegHandle->CMPA.half.CMPA++; } else { epwm_info->EPwm_CMPA_Direction = EPWM_CMP_DOWN; epwm_info->EPwmRegHandle->CMPA.half.CMPA--; } } // If we were decreasing CMPA, check to see if // we reached the min value. If not, decrease CMPA / / else, change directions and increase CMPA else { if(epwm_info->EPwmRegHandle->CMPA.half.CMPA == epwm_info->EPwmMinCMPA) { epwm_info->EPwm_CMPA_Direction = EPWM_CMP_UP; epwm_info->EPwmRegHandle->CMPA.half.CMPA++; } else { epwm_info->EPwmRegHandle->CMPA.half.CMPA--; } } // If we were increasing CMPB, check to see if // we reached the max value. If not, increase CMPB // else, change directions and decrease CMPB if(epwm_info->EPwm_CMPB_Direction == EPWM_CMP_UP) { if(epwm_info->EPwmRegHandle->CMPB < epwm_info->EPwmMaxCMPB) { epwm_info->EPwmRegHandle->CMPB++; } else { epwm_info->EPwm_CMPB_Direction = EPWM_CMP_DOWN; epwm_info- >EPwmRegHandle->CMPB--; } } // If we were decreasing CMPB, check to see if // we reached the min value. If not, decrease CMPB // else, change directions and increase CMPB else { if(epwm_info- >EPwmRegHandle->CMPB == epwm_info->EPwmMinCMPB) { epwm_info->EPwm_CMPB_Direction = EPWM_CMP_UP; epwm_info->EPwmRegHandle->CMPB++; } else { epwm_info->EPwmRegHandle->CMPB--; } } } else { epwm_info->EPwmTime rIntCount++ ; } return; }If not, increase CMPB // else, change directions and decrease CMPB if(epwm_info->EPwm_CMPB_Direction == EPWM_CMP_UP) { if(epwm_info->EPwmRegHandle->CMPB < epwm_info->EPwmMaxCMPB) { epwm_info->EPwmRegHandle->CMPB++; } else { epwm_info->EPwm_CMPB_Direction = EPWM_CMP_DOWN; epwm_info->EPwmRegHandle->CMPB--; } } // If we were decreasing CMPB, check to see if // we reached the min value. If not, decrease CMPB // else, change directions and increase CMPB else { if(epwm_info->EPwmRegHandle->CMPB == epwm_info->EPwmMinCMPB) { epwm_info->EPwm_CMPB_Direction = EPWM_CMP_UP; epwm_info->EPwmRegHandle->CMPB++; } else { epwm_info->EPwmRegHandle->CMPB- -; } } } else { epwm_info->EPwmTimerIntCount++; } return; }If not, increase CMPB // else, change directions and decrease CMPB if(epwm_info->EPwm_CMPB_Direction == EPWM_CMP_UP) { if(epwm_info->EPwmRegHandle->CMPB < epwm_info->EPwmMaxCMPB) { epwm_info->EPwmRegHandle->CMPB++; } else { epwm_info->EPwm_CMPB_Direction = EPWM_CMP_DOWN; epwm_info->EPwmRegHandle->CMPB--; } } // If we were decreasing CMPB, check to see if // we reached the min value. If not, decrease CMPB // else, change directions and increase CMPB else { if(epwm_info->EPwmRegHandle->CMPB == epwm_info->EPwmMinCMPB) { epwm_info->EPwm_CMPB_Direction = EPWM_CMP_UP; epwm_info->EPwmRegHandle->CMPB++; } else { epwm_info->EPwmRegHandle->CMPB- -; } } } else { epwm_info->EPwmTimerIntCount++; } return; }

This post is from DSP and ARM Processors

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95% duty cycle should be It refers to the positive duty cycle, 95% high level. This is related to other settings, such as whether the count value of the counter is high or low when it is equal to the value of the comparison register cmpa or cmpb. The state of this comparison is not the state of io, but a signal inside epwm. This signal also needs to be compared by other modules. See As shown in the figure below, other registers must be set. For example, the INMODE and OUTMODE settings of the DBCTL register in the DB module directly affect the logical relationship. Read the manual carefully and then look at the official routines. [attach]345093[/attach] [attach]345094[/attach] [attach]345095[/attach]   Details Published on 2018-2-23 23:49
 

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EPwm3Regs.TBPRD is the period register EPwm3Regs.CMPA.half.CMPA and EPwm3Regs.CMPB are the comparison values of the two comparators A/B respectively, which adjust the duty cycle.
This post is from DSP and ARM Processors
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elvike published on 2018-2-22 21:33 EPwm3Regs.TBPRD is the period register EPwm3Regs.CMPA.half.CMPA and EPwm3Regs.CMPB are the comparison values of the two comparators A/B respectively, ...
Hello~ Then I should put EPwm3Regs. How much should be written to CMPA.half.CMPA and EPwm3Regs.CMPB respectively? How can I see that the duty cycle is 95% on the oscilloscope? Can you teach me? Thank you
This post is from DSP and ARM Processors

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95% duty cycle should refer to positive duty cycle, 95% high level. This is related to other settings, such as whether the counter count value is high or low when it is equal to the value of the comparison register cmpa or cmpb. The comparison state is not the state of io, but the signal inside epwm. This signal also needs to be compared by other modules.  Details Published on 2018-2-23 23:49
 
 
 

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youkevin published on 2018-2-23 09:05 Hello~ How much should I write to EPwm3Regs.CMPA.half.CMPA and EPwm3Regs.CMPB? Then I can see the duty on the oscilloscope...
95% duty cycle should be It refers to the positive duty cycle, 95% high level. This is related to other settings, such as whether the count value of the counter is high or low when it is equal to the value of the comparison register cmpa or cmpb. The state of this comparison is not the state of io, but a signal inside epwm. This signal also needs to be compared by other modules. See As shown in the figure below, other registers must be set. For example, the INMODE and OUTMODE settings of the DBCTL register in the DB module directly affect the logical relationship. Read the manual carefully and then look at the official routines.
This post is from DSP and ARM Processors
Personal signature作为一个水军,就是尽量的多回帖,因为懂的技术少,所以回帖水分大,见谅!
EEWORLD开发板置换群:309018200,——电工们免费装β的天堂,商家勿入!加群暗号:喵
 
 
 

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