Hello everyone, it's time for daily learning again. Today we're going to talk about bus interfaces. 1. I2C bus The I2C bus is a serial bus launched by PHLIPS. It is a high-performance serial bus with bus arbitration and high-speed and low-speed device synchronization functions required by multi-host systems. It uses two bidirectional I/O lines: SCL (serial clock line) and SDA (serial data line). The bus is mainly used to connect the overall circuit (ICS). I2C is a multi-directional control bus, which means that multiple chips can be connected to the same bus structure, and each chip can be used as a control source for data transmission. This method simplifies the signal transmission bus. It can be connected to multiple slave devices, and can be connected to multiple slave devices. The circuit structure of the SDA and SCL pins inside each I2C bus device is the same, and the output drive of the pin is connected to the input buffer. The output is an open-drain field effect transistor, and the input buffer is a high-input impedance phase converter. This circuit has two characteristics: (1) Since SDA and SCL are open-drain structures, the "wired AND" logic of the signal is realized with the help of external pull-up resistors; (2) While the pin outputs the signal, it also detects the level on the pin to check whether it is consistent with the output just now. It provides the hardware basis for "clock synchronization" and "bus arbitration". If the slave wants the host to reduce the transmission speed, it can notify the host by actively pulling down SCL to extend its low level time. When the host finds that the SCL level is pulled low when preparing for the next transmission, it will wait until the slave completes the operation and releases the control of the SCL line. In this way, the host is actually controlled by the clock synchronization of the slave. It can be seen that the low level on the SCL line is determined by the device with the longest clock low level; the high level time is determined by the device with the shortest high level time. This is clock synchronization, which solves the speed synchronization problem of the I2C bus. 2. SPI bus The SPI (Serial Peripheral Interface) bus system is a synchronous serial peripheral interface that enables MCU to communicate with various peripheral devices in serial mode to exchange information. This interface generally uses 4 lines. The three registers of SPI are: control register SPCR, status register SPSR, and data register SPDR. The SPI interface is a synchronous serial data transmission between the CPU and peripheral low-speed devices. Under the shift pulse of the master device, data is transmitted bit by bit, with the high bit first and the low bit last. It is full-duplex communication. The data transmission speed is generally faster than the I2C bus, and the speed can reach several Mbps. SPI bus definition: (1) MOSI – master device data output, slave device data input (2) MISO – master device data input, slave device data output (3) SCLK – clock signal, generated by the master device, the maximum is fPCLK/2, the maximum slave mode frequency is fCPU/2 (4) NSS – slave device enable signal, controlled by the master device, some ICs will be marked as CS (Chip select) In point-to-point communication, the SPI interface does not require addressing operations and is full-duplex communication, which is simple and efficient. In a system with multiple slave devices, each slave device requires an independent enable signal, and the hardware is slightly more complicated than the I2C system. The internal hardware of the SPI interface is actually two simple shift registers. The data transmitted is 8 bits. Under the slave device enable signal and shift pulse generated by the master device, the data is transmitted bit by bit, with the high bit first and the low bit last. The data changes on the rising edge of SCLK, and a bit of data is stored in the shift register at the same time. SPI has four working modes, CPOL and CPHA can be 0 or 1 respectively: CPOL: (Clock Polarity), clock polarity. When CPOL is 0, the level is low when the clock is idle; when CPOL is 1, the level is high when the clock is idle; CPHA: Sad: Clock Phase. When CPHA is 0, the rising edge of the clock collects data and the falling edge of the clock cycle outputs data; when CPHA is 1, the falling edge of the clock collects data and the rising edge of the clock cycle outputs data; 3. RS232, RS422, RS485 Bus RS232: A standard asynchronous transmission interface established by the Electronic Industries Association (EIA). Usually the RS-232 interface appears in the form of 9 pins (DB-9) or 25 pins (DB-25). Generally, there are two sets of RS-232 interfaces on personal computers, called COM1 and COM2. It defines the serial connection between data terminal equipment (DTE) and data communication equipment (DCE). It is a serial communication interface standard. RS-422: It is a balanced voltage digital interface circuit. It can connect multiple receiving nodes on the same transmission line, up to 256 nodes. That is, one master device (Master) and the rest are slave devices (Slave). RS-422 supports point-to-multiple bidirectional communication. It is a parallel communication interface standard. RS485: It is a two-wire system (mostly using shielded twisted pair) transmission. It is a master-slave communication mode, that is, one host with multiple slaves. In many cases, when connecting the RS-485 communication link, it is simply to connect the "A" and "B" ends of each interface with a pair of twisted pairs. The RS485 interface connector uses a DB-9 9-pin plug socket, the RS485 interface with the intelligent terminal uses DB-9 (hole), and the keyboard interface RS485 connected to the keyboard uses DB-9 (pin). The difference between RS232, RS422 and RS485: a. The difference in communication distance: 1. RS232 can transmit up to 15 meters. 2.RS-422 is a differential mode transmission, with strong anti-interference ability and can transmit 1200 meters. 3. The maximum communication distance of RS485 is about 1219m. b. Different logical representations: 1. RS232 uses -12V to represent logic 1, 12V to represent 0, full duplex, at least 3 communication lines (RX, TX, GND), because it uses absolute voltage to represent logic, due to interference, wire resistance and other reasons, the communication distance is not far. 2. RS422 uses TTL differential level to represent logic, that is, the voltage difference between two lines represents logic. RS422 is defined as full-duplex, so at least 4 communication lines are required (usually with an additional ground line). One driver can drive up to 10 receivers (i.e., the receiver is 1/10 unit load). The communication distance is related to the communication rate. Generally, high speed can be used for communication when the distance is short, and long distance communication can be carried out when the rate is low. 3. RS485, most of them inherit 422. The main difference is that RS485 can be half-duplex, and the driving capacity of one driver can drive at least 32 receivers (i.e., the receiver is 1/32 unit load). When using a receiver with higher impedance, it can drive more receivers. Therefore, most full-duplex 485 driver/receiver pairs are now marked: RS422/485, because full-duplex RS485 driver/receiver pairs can definitely be used in RS422 networks. 4. USB USB, short for Universal Serial Bus, is an external bus standard used to regulate the connection and communication between computers and external devices. It is an interface technology used in the PC field. The USB interface supports plug-and-play and hot-swap functions of devices. USB is a unified transmission specification, but there are many types of interfaces. The most common one is the flat one used on our computers, which is called Type A port. There are 4 connecting wires in it. They are divided into male and female interfaces according to who plugs in who. Generally, the line has a male port and the machine has a female port. USB signals are transmitted using twisted pair cables marked as D+ and D-, respectively. They each use half-duplex differential signals and work together to offset the electromagnetic interference of long wires. USB1.1 is a more common USB specification, with a high-speed transmission rate of 12Mbps and a low-speed transmission rate of 1.5Mbps (b means bit), 1MB/s (megabyte/second) = 8MBPS (megabit/second), 12Mbps = 1.5MB/s. Currently, most MP3s use this type of interface. The USB2.0 specification evolved from the USB1.1 specification. Its transmission rate reaches 480Mbps, which is 60MB/s when converted to MB, which is enough to meet the speed requirements of most peripherals. The "Enhanced Host Controller Interface" (EHCI) in USB 2.0 defines an architecture that is compatible with USB 1.1. It can use USB 2.0 drivers to drive USB 1.1 devices. In other words, all devices that support USB 1.1 can be used directly on the USB 2.0 interface without worrying about compatibility issues, and accessories such as USB cables and plugs can also be used directly. 5. PCI PCI, or Peripheral Component Interconnect, is a local parallel bus standard. It was developed from the ISA bus. Structurally, PCI is a first-level bus inserted between the CPU supplier and the original system bus. A bridge circuit is used to manage this layer and implement the interface between the upper and lower levels to coordinate data transmission. The PCI bus is a tree structure and is independent of the CPU bus and can operate in parallel with the CPU bus. PCI devices and PCI bridges can be connected to the PCI bus. Only one PCI master device is allowed on the PCI bus, and the others are PCI slave devices. Read and write operations can only be performed between the master and slave devices. Data exchange between slave devices needs to be transferred through the master device. The PCI bus structure is shown in the figure below. The PCI bus is a synchronous processor-independent 32-bit or 64-bit local bus with a maximum operating frequency of 33MHz and a peak speed of 132MB/s at 32-bit and 132MB/s at 64-bit is 264MB/s, and the bus specification is published by PCISIG. Compared with the ISA bus, the PCI bus has the following significant characteristics: (1) High speed The PCI local bus operates at a clock frequency of 33MHz, using 32 bit data bus, the data transfer rate can be as high as 132MB/s, far exceeding all previous buses. In addition, the master device (Master) of the PCI bus can directly exchange data with the microcomputer memory. (2) Plug and play The hardware resources of the PCI board are uniformly allocated by the computer according to their respective requirements, and there will never be any Conflict issues. (3) Reliability Compared with the original ISA bus commonly used in microcomputers, the PCI bus adds parity errors (PERR) and system errors (SERR). , slave device end (STOP) and other control signals and timeout processing and other reliability measures greatly increase the reliability of data transmission. (4) Complexity The powerful functions of the PCI bus greatly increase the difficulty of hardware design and software development. In terms of hardware, large-capacity, high-speed CPLD or FPGA chips must be used to realize the complex functions of the PCI bus. In terms of software, according to the operating system used, software tools must be used to compile device drivers that support plug-and-play functionality. (5) Automatic configuration When a PCI card is inserted into the system, the BIOS will configure the card based on the information it reads about the card and the actual situation of the system. Allocates storage addresses, interrupts, and certain timing information. (6) Shared interrupts The PCI bus adopts an active low level mode. Multiple interrupts can share an interrupt line, while the ISA bus is an edge-triggered mode. . (7) Good scalability Since PCI is designed to assist existing expansion bus standards, it is fully compatible with ISA, EISA and MCA buses. (8) Multiplexing In order to optimize the design, the address line and the data line share a set of physical lines in the PCI bus, that is, multiplexing . The PCI connector is small in size and uses multiplexing technology to reduce the number of components and pins and improve efficiency. (9) Strict specifications The PCI bus has strict regulations on protocols, timing, electrical performance, mechanical performance and other indicators, ensuring the reliability and safety of PCI compatibility. 6. PCIE PCI-Express (peripheral component interconnect express) is a high-speed serial computer expansion bus standard. Conceptually, the PCI Express bus is a high-speed serial replacement of the older PCI/PCI-X bus. One of the main differences between the PCI Express bus and older PCI is the bus topology. PCI uses a shared parallel bus architecture in which the PCI host and all devices share a common set of address, data, and control lines. In contrast, PCI Express is based on a point-to-point topology, with a separate serial link connecting each device to the root system (host). Due to its shared bus topology, the PCI bus can be arbitrated in a single direction (in the case of multiple hosts) and is limited to one host at a time. Additionally, the old PCI clocking scheme limited the bus clock to the slowest peripheral on the bus (regardless of the devices involved in the bus transaction). In contrast, PCI Express bus links support full-duplex communication between any two endpoints, with no inherent limitations on concurrent access across multiple endpoints simultaneously. In terms of bus protocol, PCI Express communication is encapsulated in data packets. The job of packaging and unpacking data and status message traffic is handled by the PCI Express port's transaction layer, and fundamental differences in electrical signaling and bus protocols require the use of different mechanical form factors and expansion connectors (thus, a new motherboard and a new adapter board ); PCI slots and PCI Express slots are not interchangeable. At the software level, PCI Express retains backward compatibility with PCI; legacy PCI system software can detect and configure newer PCI Express devices without explicit support for the PCI Express standard, but New PCI Express features are not accessible. A PCI Express link between two devices can consist of 1 to 32 lanes. In a multi-lane link, packet data is striped across the lanes, and the peak data throughput is proportional to the overall link width. The channel count is automatically negotiated during device initialization and can be limited by either endpoint. PCI Express operates in consumer, server, and industrial applications as a motherboard-level interconnect (connecting motherboard peripherals), a passive backplane interconnect, and as an expansion card interface for add-on boards. Main applications: external GPU, storage devices, cluster interconnect. 7. Network port The network port is the rapid development of the network and has entered the G era. It is mainly divided into Gigabit Ethernet port and 100M Ethernet port. Gigabit Ethernet port is backward compatible and can also be connected to 100M Ethernet port. The RJ45 interface is a commonly used Ethernet interface that supports 10M and 100M adaptive network connection speeds. The RJ45 network cable plug is also called a crystal plug. It has eight cores and is widely used in local area networks. The connection with the network cable (called Category 5 cable or twisted pair) between the network equipment of ADSL broadband Internet users. In specific applications, there are two connection methods (line sequences) for RJ45 plugs and network cables, which are called T568A line sequence and T568B line sequence respectively. [size= 14px] There are two common types of RJ45 interfaces: DTE (data terminal equipment) type used for Ethernet network cards, router Ethernet interfaces, etc., and DCE (digital communication equipment) type used for switches, etc. When two devices of the same type use the RJ45 interface to communicate, a crossover cable must be used. If the DTE type interface and the DTE type interface do not cross the connected pins when connected, the touching pins are all data receiving (transmitting) pins, and communication cannot be carried out. In addition: some DCE type devices will automatically negotiate with the other party. At this time, either a straight-through line or a parallel line can be used for connection. This content is originally created by EEWORLD forum user 大辉哥0614. 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