Detailed explanation of embedded system knowledge and interface technology summary

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Detailed explanation of embedded system knowledge and interface technology summary [Copy link]

1. What is embedded? IEEE (Institute of Electrical and Electronics Engineers) defines embedded systems as: "Devices used to control, monitor or assist the operation of machines and equipment". The original text is: Devices Used to Control, Monitor or Assist the Operation of Equipment, Machinery or Plants). An embedded system is a special-purpose computer system that is part of a device or equipment. Generally, an embedded system is an embedded processor control board with a control program stored in ROM. In fact, all devices with digital interfaces, such as watches, microwave ovens, video recorders, cars, etc., use embedded systems. Some embedded systems also include operating systems, but most embedded systems are implemented by a single program to implement the entire control logic. Defined from the application object, an embedded system is a combination of software and hardware, and can also cover mechanical and other auxiliary devices. The generally recognized definition of embedded systems in China is: a special-purpose computer system that is application-centered, based on computer technology, with tailorable software and hardware to meet the strict requirements of the application system for function, reliability, cost, volume, power consumption, etc. An embedded system device is generally composed of an embedded computer system and an execution device. The embedded computer system is the core of the entire embedded system, consisting of a hardware layer, an intermediate layer, a system software layer, and an application software layer. The execution device is also called the controlled object, which can accept the control commands issued by the embedded computer system and perform the specified operations or tasks. The actuator can be very simple, such as a micro motor on a mobile phone, which turns on when the phone is in vibration reception mode; it can also be very complex, such as the SONY smart robot dog, which integrates multiple micro control motors and multiple sensors, so that it can perform various complex actions and sense various status information. 2. Composition of embedded systems 1. The hardware layer includes embedded microprocessors, memories (SDRAM, ROM, Flash, etc.), general device interfaces and I/O interfaces (A/D, D/A, I/O, etc.). Adding power circuits, clock circuits and memory circuits to an embedded processor constitutes an embedded core control module. Among them, the operating system and application programs can be solidified in ROM. 2. Middle layer There is a middle layer between the hardware layer and the software layer, also known as the hardware abstraction layer (HAL) or board support package (BSP). It separates the upper-level software of the semi-system from the underlying hardware, making the underlying driver of the system independent of the hardware. The upper-level software developers do not need to care about the specific situation of the underlying hardware, and can develop according to the interface provided by the BSP layer. This layer generally includes the initialization of related underlying hardware, data input/output operations and hardware device configuration functions. In fact, BSP is a software layer between the operating system and the underlying hardware, including most of the software modules in the system that are closely related to the hardware. Designing a complete BSP requires completing two parts of work: embedding the BSP function of the hardware initialization of the industrial system and designing hardware-related device drivers. 3. System Software Layer The system software layer consists of real-time multitasking operating system (RTOS), file system, and graphical user interface (GUI,GUI), network system and general component modules. RTOSis the foundation and development platform of embedded application software.

3. Real-time system

Definition: A system that can complete system functions and respond to external or internal, synchronous or asynchronous time within a specified or determined time.

Difference: General systems generally pursue the average response time of the system and the convenience of users;while real-time systems mainly consider the system behavior in the worst case.

Characteristics: time constraints, predictability, reliability, and interactivity with the external environment.

Hard real-time(Strong real-time): refers to the time requirements of applications that should be fully met, otherwise it will cause major safety accidents, or even cause major loss of life and property and ecological damage, such as: aerospace, military.

Soft real-time(Weak real-time): refers to some applications that have time requirements, but occasional violations of real-time tasks will not cause serious impact on system operation and environment, such as: monitoring systems, real-time information collection systems.

Task constraints include: time constraints, resource constraints, execution order constraints and performance constraints.

4. Scheduling of real-time systems

Scheduling: Given a set of real-time tasks and system resources, determine the entire process of when and where each task is executed.

Preemptive scheduling: Usually priority-driven scheduling, such as uCOS. The advantages are good real-time performance and fast response. The scheduling algorithm is relatively simple and can guarantee the time constraints of high-priority tasks ; The disadvantage is that there are many context switches.

Non-preemptive scheduling: Usually scheduling allocated by time slices. Tasks are not allowed to be interrupted during execution. Once a task occupies the processor, it must be completed or voluntarily abandoned, such as WinCE. The advantage is less context switching; the disadvantage is low processor resource utilization and poor schedulability. Static table driven strategy: Before running, the system uses a search strategy to generate a running schedule based on the time constraints and associations of each task, indicating the starting time and running time of each task. Priority driven strategy: Determine the execution order of tasks according to their priorities. Real-time task classification: periodic tasks, occasional tasks, and non-periodic tasks. General structural model of real-time system: data acquisition tasks realize the collection of sensor data, data processing tasks process the collected data, and send the processed data to the execution agency management task control agency for execution.

5. Embedded microprocessor architecture

Von Neumann architecture: Programs and data share a storage space, program instruction storage address and data storage address point to different physical locations of the same memory, using a single address and data bus, program and data have the same width. For example: 8086, ARM7, MIPS…

Harvard architecture: Programs and data are two independent memories, each memory is independently addressed and accessed, it is a memory structure that separates program storage and data storage. For example: AVR, ARM9, ARM10… Comparison of the characteristics of CISC and RISC. The time P required for a computer to execute a program can be calculated using the following formula: P=I×CPI×T I: The number of instructions that a high-level language program runs on a machine after being compiled. CPI: The average number of cycles required to execute each instruction. T: The time for each machine cycle. The idea of pipeline: to change the serial execution process of an instruction in the CPU into several sub-processes of instructions, which are executed overlappingly in the CPU. Pipeline indicators: Throughput: the number of results that flow out of the pipeline processor per unit time. If the sub-processes of the pipeline take different lengths of time, the throughput should be the reciprocal of the longest sub-process. Establishment time: the time when the pipeline starts working and reaches the maximum throughput. If the time taken by m subprocesses is the same, which is t, then the establishment time T = mt. The byte order of information storage A. Memory unit: byte (8 bits) B. Word length determines the addressing capability of the microprocessor, that is, the size of the virtual address space.=left]C. The virtual address space of a 32-bit microprocessor is 232 bits, or 4GB.

D. Little-endian byte order: the low byte is at the low address of the memory, and the high byte is at the high address of the memory.

E. Big-endian byte order: the high byte is at the low address of the memory, and the low byte is at the high address of the memory.

F. The storage order of network devices depends on the data link layer at the bottom of the OSI model.

6. Basics of Logic Circuits

Based on whether the circuit has a storage function, the logic circuit is divided into: combinational logic circuit and sequential logic circuit.

Combinatorial logic circuit: The output of the circuit at any time depends only on the input signal at that time, and has nothing to do with the state of the circuit before the input signal acts. Commonly used logic circuits include decoders and multiplexers.

Sequential logic circuit: The output of the circuit at any time is not only related to the input at that time, but also to the state of the circuit at that time. Therefore, the sequential circuit must contain memory elements. The trigger is the basis of the sequential logic circuit. Commonly used sequential logic circuits include registers and counters.

The concepts of truth table, Boolean algebra, Morgan's law, and gate circuit. The gate circuits of NOR (Nor) and NAND (Nand) are called universal gate circuits, which can realize any kind of logic function. Decoder: a combinational logic network with multiple inputs and multiple outputs. For each input of an n-bit binary code, at most one of the m output terminals is valid. When m=2n, it is full decoding; when m<2n, it is partial decoding. Since the high-level output current of the integrated circuit is small, while the low-level output current is relatively large, when the integrated gate circuit is used to directly drive the LED, the low-level drive method is often used. The seven-segment character display LCD uses the different optical properties of the liquid crystal with and without an external electric field to display characters. The clock signal is the basis of sequential logic, which is used to determine the appropriate update of the state in the logic unit. Synchronization is the main constraint in the clock control system. When selecting a trigger, the trigger mode must be considered. There are two trigger modes: Level trigger mode: It has the advantage of simple structure and is often used to form a register. Edge trigger mode: It has a strong ability to resist data end interference and is often used to form registers, counters, etc. 7. Bus circuit and signal drive The bus is a collection of various signal lines and is a common channel for transmitting data, address and control information between components in an embedded system. At the same time, each channel line can transmit a binary signal. According to the type of information transmitted by the bus, it can be divided into: data bus (DB), address bus (AB) and control bus (CB). Main parameters of the bus: Bus bandwidth: The amount of data that can be transmitted on the bus within a certain period of time, generally expressed in MByte/s. Bus width: The number of data bits that the bus can transmit at the same time (bit), that is, the concepts of bus width such as 32 bits and 64 bits, also called bus width. The wider the bus width, the greater the data transmission rate per second, that is, the wider the bus bandwidth. Bus frequency: The working clock frequency is in MHz. The higher the working frequency, the faster the bus works, that is, the wider the bus bandwidth. Bus bandwidth = Bus width × Bus frequency / 8,The unit is MBps. Common buses: ISA bus, PCI bus, IIC bus, SPI bus, PC104 bus and CAN bus, etc. Only devices with three-state outputs can be connected to the data bus, and the commonly used three-state gate is the output buffer.

When the load connected to the bus exceeds the load capacity of the bus, a buffer or driver must be added between the bus and the load. The most commonly used is a three-state buffer, which is used for driving and isolation.

The use of bus multiplexing technology can realize the sharing of data bus and address bus. But it will bring two problems:

AIt is necessary to add external circuits to multiplex and decouple bus signals, such as address latches.

BThe bus speed is lower than that of non-multiplexed bus systems.

Two types of bus communication protocols: synchronous mode and asynchronous mode.

The solution to the bus arbitration problem is based on the concept of priority (priority ). 8. Level conversion circuit Digital integrated circuits can be divided into two categories: bipolar integrated circuits (TTL) and metal oxide semiconductors (MOS). CMOS circuits are widely used because of their extremely low static power consumption, high operating speed and strong anti-interference ability. The way to solve the difficulty of interfacing TTL and CMOS circuits is to connect a pull-up resistor R between the output end of the TTL circuit and the power supply. The value of the pull-up resistor R is determined by the high-level output leakage current IOH of the TTL. Different series of TTL should use different R values.

IX. Information Representation and Operational Basis in Embedded Systems

Positional Counting System and Conversion: This is relatively simple, but you should also know how to convert, as there is a possibility of questions.

Number Representation in Computers: Source Code, Inverse Code and Complement Code.

The inverse code of a positive number is the same as the source code, and the inverse code of a negative number is the source code of the number, except for the sign bit.

The complement code of a positive number is the same as the source code, and the complement code of a negative number is the inverse code of the number plus one. For example, the source code of -98: 11100010B, the inverse code: 10011101B, the complement code: 10011110B, the fixed-point representation: the position of the decimal point of a number is fixed by artificial agreement. Floating-point representation: the position of the decimal point of a number is floating, and it consists of the mantissa and the exponent. Any binary number N can always be written as: N=2P×S. S is the mantissa, P is the order. Chinese character representation, figure out the transformation between GB2318-80 Chinese standard code and machine code. Waveform quantization parameters in speech coding (may give a simple calculation question) Sampling frequency: the number of samples in one second, reflects the interval size between sampling points. The upper limit of human hearing is 20kHz, so sampling frequencies above 40kHz are enough to satisfy people. The sampling frequency used by CD records is 44.1kHz. Measurement accuracy: the quantization level of the sample. Currently, the standard sampling levels are 8 bits and 16 bits. Number of channels: mono and stereo. Stereo requires twice the storage space. 10. Error control coding According to the function of the code group, it can be divided into error detection code and error correction code. Error detection code refers to the code that can automatically detect errors, such as parity check code; error correction code refers to the code that can not only detect errors but also automatically correct errors, such as cyclic redundancy check code. Parity check code, Hamming code, cyclic redundancy check code (CRC). XI. Measurement items of embedded systems Performance indicators: divided into component performance indicators and comprehensive performance indicators, mainly including: throughput, real-time and various utilization rates. Reliability and security Reliability is the most important and prominent basic requirement of embedded systems. It is the guarantee for the normal operation of an embedded system. It is generally measured by the mean time between failures MTBF. Maintainability: generally expressed by the mean time to repair MTTR.

Availability

Power consumption

Environmental adaptability

Versatility

Security

Confidentiality

Scalability

The price in the cost-effectiveness ratio, in addition to the direct purchase price of the embedded system, should also include the installation cost, several years of operation and maintenance costs and software rental fees.

Evaluation methods for embedded systems: measurement method and model method

The measurement method is the most direct and basic method, which needs to solve two problems:

ADetermine the system parameters to be measured according to the purpose of the study.

BSelect the measurement tools and methods.

There are two measurement methods: sampling method and event tracking method.

The model method is divided into analytical model method and simulation model method. The analytical model method uses some mathematical equations to characterize the system model, while the simulation model method uses the running of the simulation program to dynamically express the state of the embedded system, and conducts system statistical analysis to obtain performance indicators.

The most commonly used queuing model in the analytical model method is the queuing model, which includes three parts: input flow, queuing rules and service mechanism. Using models to evaluate systems requires solving three problems: designing models, solving models, calibrating and verifying models. 12. Interface technology Flash memory (1) Flash memory is a non-volatile memory. It can be divided into NOR Flash and NAND Flash according to its structure. (2) Characteristics of Flash memory: A. Block structure: It is physically divided into several blocks, which are independent of each other. B. Erase before writing: Flash write operation can only write data bits from 1 to 0, but not from 0 to 1. Therefore, before writing to the memory, an erase operation must be performed to initialize the pre-written data bits to 1. The minimum unit of an erase operation is a block, not a single byte. C. Operation instructions: To perform a write operation, it must enter a string of special instructions (NOR Flash) or complete a sequence (NAND Flash) to write data. D. Bit reversal: Due to the inherent characteristics of Flash, one or more bits of data errors may occasionally occur during the reading and writing process. E. Bad block: Once a block is damaged, it cannot be repaired. The result of operating a damaged block is unpredictable. (3) Features of NOR Flash: Applications can be run directly in the flash memory without having to read the code into the system RAM for execution.Flash has a high transmission efficiency and is very cost-effective when used in small capacities of 1MB to 4MB. However, its low write and erase speeds greatly affect its performance. (4) Characteristics of NAND Flash It can increase extremely high density units, achieve high storage density, and has very fast write and erase speeds. This is why all USB flash drives use NAND Flash as storage media. The difficulty in using NAND Flash is that flash memory requires a special system interface. (5) The difference between NOR Flash and NAND Flash: A. The read speed of NOR Flash and NAND Flash is slightly faster than that of NAND Flash. B. The erase and write speed of NAND Flash are much faster than that of NOR Flash. C. The random read capability of NAND Flash and NOR Flash is poor, so they are suitable for continuous reading of large amounts of data. D and NOR Flash have SRAM interfaces, which have enough address inputs for addressing, and can easily access every byte inside. The address, data, and command of NAND Flash share an 8-bit bus (some companies' products use 16-bit), and each read and write requires a complex I/O interface to serially access data. The capacity of E and NOR Flash is generally small, usually between 1MB and 8MB; NAND Flash is only used in products with 8MB or more. Therefore, NOR Flash is only used in code storage media, and NAND Flash is suitable for data storage. The maximum number of erase and write times for each block in F and NAND Flash is one million, while that for NOR Flash is one hundred thousand. G and NOR Flash can be connected like other memories, used very directly, and code can be run directly on them; NAND Flash requires a special I/O interface, and when it is used, a driver must be written before other operations can be continued. Because designers must never write to bad blocks, this means that virtual imaging must be performed on NAND Flash from beginning to end. H, NOR Flash is used in code storage, communication products, network processing and other fields that require high data reliability, and is called code flash memory; NANDFlash is used in MP3, memory cards, USB flash drives and other fields that require high storage capacity, and is called data flash memory. 2. RAM memory (1) Characteristics of SRAM: SRAM stands for static random access memory. It will keep a value as long as it is powered. It has no refresh cycle and is composed of triggers as basic units. It has low integration. Each SRAM storage unit consists of 6 transistors, so its cost is relatively high. It has a high speed and is often used in high-speed cache memory.

Usually

SRAMhas4pins:

CE: Chip select signal, low level is valid.

R/W: Read and write control signal.

ADDRESS: A group of address lines.

DATA: A group of bidirectional signal lines for data transmission.

(2) Characteristics of DRAM:

DRAM stands for dynamic random access memory. This is a semiconductor memory that stores data in the form of electric charge. Each of its storage cells consists of a transistor and a capacitor, and data is stored in the capacitor. Capacitors lose charge due to leakage, so DRAM devices are unstable. They must be refreshed regularly to keep data in memory. The interface of DRAM is relatively complex, usually with the following pins: CE: chip select signal, low level is valid. R/W: read and write control signal. RAS: row address select signal, usually connected to the high part of the address. CAS: column address select signal, usually connected to the low part of the address. ADDRESS: a group of address lines. DATA: A set of bidirectional signal lines used for data transmission. (3) Characteristics of SDRAM: SDRAM stands for Synchronous Dynamic Random Access Memory. Synchronous means that the memory needs a synchronous clock to work, and the internal command transmission and data transmission are based on it; dynamic means that the memory array needs to be constantly refreshed to ensure that data is not lost. It can usually only work at a main frequency of 133MHz. (4) Characteristics of DDRAM DDRAM stands for Double Data Rate Synchronous Dynamic Random Access Memory, also known as DDR. DDRAM is based on SDRAM technology. SDRAM transmits data only once in one clock cycle, and it transmits data during the rising period of the clock; while DDR memory transmits data twice in one clock cycle, and it can transmit data once during the rising period and once during the falling period of the clock. At the main frequency of 133MHz, the memory bandwidth of DDR can reach 133×64b/8×2=2.1GB/s. 3、hard disk、CD、CF card、SD card4、GPIO principle and structureGPIO is the most basic form of I/O, which is a group of input pins or output pins. Some GPIO pins can be programmed to change the working direction. There are usually two control registers: data register and data direction register. The data direction register sets the direction of the port. If the pin is set as output, the data register will control the state of the pin. If the pin is set as input, the state of the input pin is controlled by the logic circuit layer on the pin. 5. A/D interface (1) A/D converter is a circuit that converts electrical analog quantity into digital quantity. There are many ways to achieve A/D conversion, and the commonly used methods are counting method, double integration method and successive approximation method. (2) Counting A/D conversion method The main components of the circuit include: comparator, counter, D/A converter and standard voltage source. To put it simply, its working principle is that there is a counter which starts counting from 0 and adds 1. Each time it adds 1, the value is used as the input of the D/A converter, which generates a comparison voltage VO to compare with the input analog voltage VIN. If VO is less than VIN, then continue to count by 1 until VO is greater than VIN. At this time, the accumulated value of the counter is the output value of the A/D converter. This conversion method is simple, but slow, especially when the analog voltage is high, the conversion speed is even slower. For example, for an 8-bit A/D converter, if the input analog value is the maximum value, the counter must count from 0 to 255, and perform 255 D/A conversions and voltage comparisons to complete the conversion. (3) Double-integral A/D conversion method The main components of the circuit include: integrator, comparator, counter and standard voltage source. Its working principle is that the circuit first integrates the input voltage to be measured for a fixed time, and then converts it to the standard voltage for reverse integration with a fixed slope. After a certain period of time, the reverse integration returns to the starting value. Due to the use of a fixed slope, the time for reverse integration of the standard voltage is proportional to the input analog voltage value. The larger the input analog voltage, the longer the time it takes for the reverse integration to return to the starting value. As long as the time spent on reverse integration is measured with a standard high-frequency clock pulse, the digital value corresponding to the input analog voltage can be obtained, and the A/D conversion is completed. Its characteristics are that it has a strong ability to resist power frequency interference and high conversion accuracy, but the conversion speed is slow. Usually the conversion frequency is less than 10Hz. It is mainly used in digital test instruments, temperature measurement, etc. (4) Successive approximation A/D conversion method The main components of the circuit include: comparator, D/A converter, successive approximation register and reference voltage source. Its working principle is essentially the bisection search method, which is the same as the principle of using a balance. When performing A/D conversion, the D/A converter increases the conversion bit bit by bit from high to low, generating different output voltages, and compares the input voltage with the output voltage to achieve this. First, make the highest bit 1, which is equivalent to taking out 1/2 of the reference voltage and comparing it with the input voltage. If the input voltage is less than 1/2 of the reference voltage, the highest bit is 0, otherwise it is 1. After that, the second highest bit is 1, which is equivalent to taking out 1/2 of the reference voltage and comparing it with the input voltage. If the input voltage is less than 1/2 of the reference voltage, the highest bit is 0, otherwise it is 1.The search is then performed in half in the range of 1/2, and so on, approaching successively. Its characteristics are fast speed and high conversion accuracy. It only needs M clock pulses to complete the N-bit A/D converter. It can generally be used to measure the changes of the transition process of tens to hundreds of microseconds. It is the most commonly used conversion method at present. (5) Important indicators of A/D conversion (some simple calculations may be required) A. Resolution: reflects the ability of the A/D converter to respond to small changes in input, usually expressed by the analog voltage level corresponding to the lowest bit of the digital output (LSB). An n-bit A/D converter can reflect 1/2n full-scale analog input levels. B. Range: The range of analog input voltage that can be converted, divided into unipolar and bipolar types. C. Conversion time: The time required to complete an A/D conversion, the reciprocal of which is the conversion rate. D. Accuracy: Accuracy and resolution are two different concepts. Even if the resolution is very high, the accuracy may not be high enough due to temperature drift, linearity and other reasons. Accuracy can be expressed in two ways: absolute accuracy and relative accuracy. Absolute accuracy is usually expressed as a fraction of the least significant bit LSB of the digital quantity, and relative accuracy is expressed as a percentage of the full range of the analog voltage. For example, if the full scale is 10V and the 10-bit A/D chip has an absolute accuracy of ±1/2LSB, the quantization unit of the least significant bit LSB is: 10/1024=9.77mv, the absolute accuracy is 9.77mv/2=4.88mv, and the relative accuracy is: 0.048%]. 6. Basics of D/A Interface (1) D/A converter converts digital quantity into analog quantity. (2) In integrated circuits, T-type network is usually used to convert digital quantity into analog current, and then operational amplifier converts analog circuit into analog voltage. D/A conversion actually requires the above two links.

(3) Classification of D/A converters:

A, voltage output type: often used as high-speed D/Aconverter.

B, current output type: generally used with an external operational amplifier.

C, multiplication type: can be used as a modulator and digitally attenuate the input signal.

(4) Main indicators of D/A converters: resolution, settling time, linearity, conversion accuracy, temperature coefficient.

7, keyboard interface

(1) Two forms of keyboards: linear keyboard and matrix keyboard.

(2)There are usually two methods to identify closed keys on the keyboard: row scanning method and row inversion method.

(3)The row scanning method is a commonly used method to identify matrix keyboard keys. This method is divided into two steps:

AIdentify which column of the keyboard key is pressed: set all row lines to low level, and check whether the level of each column line is low. If a column line is low, it means that a key in this column is pressed, otherwise it means that no key is pressed.

BIf a key is pressed in a column, identify which row of the keyboard is pressed: set the level low row by row, and set the remaining rows to high level, and check the changes of each column. If the column level becomes low, it can be determined that the key at the intersection of this row and column is pressed. 8. Display interface The basic principle of LCD is to control the passage of light through different liquid crystal units by supplying power to them, so as to achieve the purpose of display. There are two ways to provide light source for LCD: projection and reflection. The LCD display of a laptop is projection type, with a light source behind the screen, so the external environment does not need a light source. The LCD used on general microcontrollers is reflection type, which requires external power supply and works by reflected light. Electroluminescence (EL) is a way for LCD screens to provide light source. According to the liquid crystal driving method, common LCD can be divided into three categories: twisted nematic (TN), super twisted nematic (STN) and thin film transistor (TFT). There are two types of LCD sold on the market: LCD display modules with driving circuits, which only need bus driving; LCD displays without driving circuits use controller scanning.

Usually, when the LCD controller is working, it requests the bus through DMA and directly reads the data at the specified address (display buffer) through SDRAM controller. This data is converted into LCD screen scanning data format by LCD controller and directly drives the LCD display. The VGA interface is essentially an analog interface, and generally uses a unified 15-pin interface, including two NC signals, three display data buses, and a The 16-bit 4-bit 4-bit RS485 interface has 5 GND signals, 3 RGB color components, 1 horizontal sync signal and 1 vertical sync signal. The level standard used by the color components is the RS343 standard defined by EIA. 9. Touch screen interface (1) According to the working principle, touch screens can be divided into: surface acoustic wave screen, capacitive screen, resistive screen and infrared screen.ft](2)The touch screen is controlled by a professional chip, such asADS7843.

10、Audio interface

(1)Basic principle: The data input by the microphone is decoded by the audio codec to complete the A/D conversion. The decoded audio data is sent to the DSP orCPU through the audio controller for corresponding processing. Then the data is sent to the audio encoder through the audio controller and output by the speaker after encodingD/A. (2) There are many digital audio formats, the most commonly used are the following three: A. Digital Audio (PCM): This is the data format used by CD or DVD. Its sampling frequency is 44.1kHz. When the precision is 16 bits, the PCM audio data rate is 1.41 Mb/s; when the precision is 32 bits, it is 2.42Mb/s. A 700MB CD can hold approximately 60 minutes of music in 16-bit PCM data format. B, MPEG layer 3 audio (MP3): the audio format used by MP3 players. The data rate of stereo MP3 is 112kb/s to 128kb/s. C, ATSC digital audio compression standard (AC3): digital TV, HDTV and movie digital audio coding standard. The data rate of stereo AC3 after encoding is 192kb/s. (3)IIS is a serial audio digital interface commonly used for encoding or decoding audio data. The IIS bus only processes sound data, and other control signals need to be transmitted separately. IIS uses three serial buses: data line SD, field selection line WS, and clock signal line SCK. (4)When the data field widths of the receiver and sender are different, the sender does not consider the data field width of the receiver. If the data field sent by the sender is smaller than the system field width, it will be padded with 0 in the lower position; if the data width of the sender is larger than the width of the receiver, the part exceeding the LSB will be truncated. The field selection WS is used to select the left and right channels. WS=0 means selecting the left channel; WS=1 means selecting the right channel. In addition, WS allows the receiving device to store the previous byte and prepare to receive the next byte. 11. Serial interface (1) Serial communication refers to the communication that is achieved by transmitting data one bit at a time. Compared with parallel communication, serial communication has the advantages of fewer transmission lines and low cost, and is particularly suitable for long-distance transmission; its disadvantage is that it is slow. (2) There are three basic communication modes for serial data transmission: simplex, half-duplex, and full-duplex. (3) Serial communication can be divided into two modes in terms of information format: synchronous communication and asynchronous communication. A. Asynchronous transmission: Each character is transmitted as an independent message and is transmitted in a fixed and predetermined sequence, but the sequence between characters depends on the arbitrary sequence between characters. In asynchronous communication, characters are transmitted frame by frame, and the transmission of each frame of characters is synchronized by the start bit. The interval between each code of a frame of data is fixed, while the time interval between two adjacent frames of data is not fixed. B. Synchronous transmission: The synchronous method is not only synchronized between characters, but also synchronized between the sequence between characters. That is, the synchronous method is to combine many characters into a character block, and then add 1 to 2 synchronization characters before each block of information, and then add appropriate error detection data after the character block before transmission. (4) Asynchronous communication must follow the following three provisions: A. Character format: start bit + data + check bit + stop bit (check bit is optional), low bit is transmitted first. B. Baud rate: the number of bits transmitted per second. C. Check bit: parity check. a. Odd check: Make sure the character has an odd number of "1"s added to the check digit. b. Even check:To ensure that the character plus the check bit has an even number of "1"s. (5) Electrical characteristics of RS-232C: negative logic. A, on TxD and RxD: logic 1 is -3V~-15V, logic 0 is 3V~15V. B, on TES, CTS, DTR, DCD and other control lines: the signal is valid (ON state) is 3V~ nt]15V, the signal is invalid(OFFstate)is-3V～-15V

(6)The level conversion between TTLstandard andRS-232Cstandard is realized by using the integrated chipRS232. (7) RS-422 serial communication interface A RS-422 is a unidirectional, balanced transmission specification with a single machine sending and multiple machines receiving. The transmission rate can reach 10Mb/s. B RS-422 uses differential transmission, also known as balanced transmission, using a pair of twisted pair cables. C RS-422 requires a terminal resistor, whose resistance is approximately equal to the characteristic impedance of the transmission cable. (8) RS-485 serial bus interface A RS-485 is a standard established on the basis of RS-422, adding multi-point and bidirectional communication capabilities, and the communication distance can be from tens of meters to thousands of meters. B RS-485 transceivers use balanced transmission and differential reception, and have the ability to suppress common-mode interference. C RS-485 requires two terminal resistors. In short distance transmission (less than 300m), terminal resistance is not required. 12, parallel interface The data transmission rate of parallel interface is 8 times faster than that of serial interface. The data transmission rate of standard parallel interface is 1Mb/s. It is generally used to connect printers, scanners, etc., so it is also called print port. Parallel interfaces can be divided into SPP (Standard Parallel Port), EPP (Enhanced Parallel Port) and ECP (Extended Parallel Port). Parallel buses are divided into standard and non-standard categories. Commonly used parallel standard buses include IEEE 488 bus and ANSISCSI bus. MXI bus is a high-performance non-standard general-purpose multi-user parallel bus. 13, PCI interface PCI bus is a high-performance 32-bit and 64-bit bus with address and data multiplexing. It is the interconnection mechanism between the microprocessor and peripheral control components and peripheral add-on boards. From the perspective of data width, PCI defines a 32-bit data bus, which can be expanded to 64 bits. From the perspective of bus speed, there are two types: 33MHz and 66MHz. Compared with the ISA bus, the address bus and data bus of the PCI bus are time-division multiplexed, supporting plug-and-play, interrupt sharing and other functions. 14、USB interface(1)Main features of USB bus: A、Easy to use, plug and play. B、Each USB system has a host, and up to 127 devices can be connected to this USB network. C、Wide application range, supports multiple devices to operate simultaneously.

D, low-cost cables and connectors, using a unified 4pin plug.

E, strong error correction capability.

F, low protocol overhead brings high bus performance, and is suitable for the development of low-cost peripherals.

G, supports multi-data stream and multi-message stream transmission between the host and the device, and supports synchronous and asynchronous transmission types.

H, bus power supply, can provide 5V/100mApower for the device. (2) The USB system is described by three parts: the USB host, the USB device, and the USB interconnect. (3) The USB bus supports three data transfer rates: high-speed signaling bit transfer rate of 480Mb/s; full-speed signaling bit transfer rate of 12Mb/s; full-speed signaling bit transfer rate of 1.5Mb/s.

(4)The USB bus cable has 4 wires: a pair of twisted signal wires and a pair of power wires.

(5)USB is a polling bus, and all data transfers are initiated by the host controller. The peripherals connected to the USB share the USB bandwidth through a token-based protocol scheduled by the host. (6) Most bus transactions involve the transmission of three packets: A. Token packet: indicates what transaction is to be performed on the bus, the USB device to be addressed, and the direction of data transfer. B. Data packet: transfers data or indicates that it has no data to transfer. C. Handshake packet: indicates whether the transfer was successful. (7) The USB data transfer model between the host and the device endpoint is called a pipe. There are two types of pipes: stream and message. Message data has a structure defined by USB, but data streams do not. (8) The transaction scheduler allows flow control for certain stream pipes. At the hardware level, the data transfer rate is adjusted by using the NAK (Negative Acknowledgement) handshake signal to prevent buffer overflow or underflow. (9) The biggest feature of USB devices is plug and play. (10) Working principle: When a USB device is inserted into a USB endpoint, the host communicates with the device's endpoint 0 through the default address 0. In this process, the host sends a series of standard requests to try to obtain descriptors. Through these requests, the host obtains all the device information it is interested in, thereby knowing the device's status and how to communicate with the device. The host then sends a SetAddressRequest to set a unique address for the device. In the future, the host will communicate with the device through the address set for the device, instead of using the default address0.

15、Interface

SPI is a synchronous protocol interface. All transmissions refer to a common clock. This synchronous clock is generated by the host. The peripheral receiving data uses the clock to synchronize the reception of the serial bit stream.

When multiple devices are connected to the sameSPIinterface of the host, the host selects them through the chip select pin of the slave device. SPI mainly uses 4 signals: master output/slave input (MOSI), master input/slave output (MISO), serial clock SCLK and peripheral chip select CS. Both the host and the peripheral contain a serial shift register. The host initiates a data transfer by writing a byte to its SPI serial register. The register transfers the byte to the peripheral through the MOSI signal line, and the peripheral also returns the contents of its shift register to the host through the MISO signal line. In this way, the contents of the two shift registers are exchanged. The write operation and read operation of the peripheral are completed synchronously, so SPI becomes a very effective protocol. If only a write operation is performed, the host only needs to ignore the received byte; conversely, if the host wants to read a byte from the peripheral, it must send a null byte to trigger the transmission of the slave. 16, IIC interface IIC bus is a high-performance multi-master bus with bus arbitration and high-speed and low-speed device synchronization. The IIC bus requires two lines: serial data line SDA and serial clock line SCL. Each device on the bus has a unique address for identification, and each device can act as a transmitter or receiver (determined by the function of the device) IIC bus has 4 operation modes: master send, master receive, slave send, slave receive. IIC has 3 types of signals in the data transmission process: A, start signal: when SCL is low, SDA jumps from high to low. B. End signal: When SCL is at a low level, SDA jumps from low to high. C. Acknowledge signal: After receiving 8 bits of data, the receiver sends a characteristic low level to the sender in the 9th pulse. After the master device sends a start signal, it will also immediately send a slave address to notify the slave device that will communicate data with it. A byte address includes 7 bits of address information and 1 bit of transmission direction indication. If the 7th bit is 0, it means a write operation is to be performed. If it is 1, it means a read operation is to be performed. Each byte transmitted on the SDA line is 8 bits long. There is no limit on the number of bytes transmitted each time. The first byte after the start signal is the address field, and each transmission byte is followed by an acknowledge bit (ACK). The MSB (high bit of the byte) of the serial data in the transmission is sent first. If the data receiver can no longer receive more data, it can interrupt the transmission by keeping SCL at a low level, which can force the data sender to wait until SCL is released again. In this way, high and low speed devices can be synchronized.n=left]The working process of IIC bus: SDA and SCL are both bidirectional. When idle, SDA and SCL are both high level. Only when SDA becomes low level and then SCL becomes low level again, the data transmission of IIC bus starts. Each bit transmitted on the SDA line is sampled at the rising edge of SCL. The bit must remain valid until SCL becomes low again, and then SDA transmits the next bit just before SCL becomes high again. Finally, SCL changes back to high, and then SDA also changes to high, indicating the end of data transmission. 17. Ethernet interface The most commonly used Ethernet protocol is IEEE802.3 standard. Transmission coding (both in 2006 and 2007): Manchester coding and differential Manchester coding. A. Manchester coding: There is a level jump in the middle of each bit. The jump from high to bottom represents "0", and the jump from low to high represents "1". B. Differential Manchester coding: There is a level jump in the middle of each bit, and the presence or absence of a jump at the beginning of each code element is used to represent "0" or "1". If there is a jump, it will become "0", and if there is no jump, it will become "1". In contrast, Manchester coding is simple, and differential Manchester coding provides better noise suppression performance. Features of Ethernet data transmission: A. The transmission of all data bits starts from the low bit, and the transmitted bit stream uses Manchester coding. B. Ethernet is a bus multiplexing method based on collision detection, which is automatically executed by hardware. C. The length of the transmitted data, destination address DA+source address SA+type field TYPE+data segment DATA+padding bit PAD, the minimum is 60B, the maximum is 1514B. D. Usually, Ethernet cards can receive data from three types of addresses: broadcast address, multicast address, and own address. E. The physical addresses of any two network cards are different and unique in the world. Network card addresses are assigned by a special organization. There are two ways to implement embedded Ethernet interface: A. Embedded processor + network card chip (e.g. RTL8019AS, CS8900, etc.) B. Processor with Ethernet interface. TCP/IP is a layered protocol, which is divided into physical layer, data link layer, network layer, transport layer and application layer. Each layer implements a clear function, corresponding to one or several transport protocols, and each layer is implemented as an independent data packet relative to its lower layer. The protocols on each layer are as follows: A, Application layer: BSD socket. B, Transport layer: TCP, UDP. C, Network layer: IP, ARP, ICMP, IGMP. D, Data link layer: IEEE802.3 EthernetMAC E, physical layer: binary bit stream. ARP (Address Resolution Protocol) A, the network layer uses 32-bit addresses to identify different hosts (that is, IP addresses), while the link layer uses 48-bit physical addresses (MAC) to identify different Ethernet or token ring interfaces. B. ARP Function: To achieve the conversion from IP address to the corresponding physical address. ICMP (Internet Control Message Protocol) A. The IP layer uses it to exchange error messages and other important control information with other hosts or routers. B. ICMP messages are transmitted in IP data packets. C, network diagnostic tools ping and traceroute are actually ICMP protocols. IP (Internet Protocol) A and IP work at the network layer and are the core protocols in the TCP/IP protocol suite. B, all TCP, UDP, ICMP and IGMP data are transmitted in IP packet format. C TTL (Time to Live field): specifies the lifetime of the IP packet (the number of routers the packet can pass through). D IP provides unreliable, connectionless packet transmission services, which are efficient and flexible. a. Unreliable: It cannot guarantee that the data packet can successfully reach the destination. Any required reliability must be provided by the upper layer (such as TCP). If an error occurs, IP has a simple error handling algorithm---discard the data packet and then send an ICMP message to the source. b. Connectionless: IP does not maintain any status information about subsequent data packets. Each data packet is processed independently. IP packets can be received out of order. (10) TCP (Transmission Control Protocol) TCP is a connection-oriented reliable transport layer protocol that provides highly reliable end-to-end data communication between two hosts. (11) UDP (User Datagram Protocol) UDP is a connectionless and unreliable transport layer protocol that does not guarantee that packets can reach their destination. Reliability is provided by the application layer. UDP has less overhead and is more suitable for use in low-end embedded applications than TCP. (12) Port: TCP and UDP use 16-bit port numbers to identify upper-layer users, i.e., application layer protocols. For example, the TCP port number for FTP services is 21.The TCP port numbers of the Telnet service are both 23, and the UDP port numbers of the TFTP service are both 69. 18. CAN bus interface CAN (Control Area Network) bus is a multi-master serial communication bus. It is one of the most widely used field buses in the world. It was originally used for electronic control networks in automotive environments. Ideally, any number of nodes can be connected to a single network composed of a CAN bus. In actual applications, node data is limited by the electrical characteristics of the network hardware. Bus signals are transmitted using differential voltages. The two signal lines are called CAN_H and CAN_L. Their static state is about 2.5V. At this time, the state represents logic 1, which can also be called "recessive". Using CAN_H higher than CAN_L to represent a logic 0 is called "dominant". At this time, the voltage values are usually CAN_H=3.5V and CAN_L=1.5V.

When the “dominant” and “recessive” bits are sent at the same time, the final bus value will be “dominant”. This feature lays the foundation for the arbitration of the CAN bus.

A bit time of CAN bus can be divided into 4 parts: synchronization segment, propagation time segment, phase buffer segment 1 and phase buffer segment 2.

The data frame of CAN bus has two formats: standard format and extended format. Including: frame start, arbitration field, control field, data field, CRC field, ACK field and frame end. The CAN bus hardware interface includes: CAN bus controller and CAN transceiver. The CAN controller mainly completes the tasks such as timing logic conversion, such as Philips' SJA1000. The CAN transceiver is the physical layer chip of the CAN bus, which realizes the conversion from TTL level to CAN bus level characteristics, such as TJA1050. 19、xDSL interface xDSL (digital subscriber line) technology is to connect dedicated DSL modulation and demodulation equipment to both sides of the existing user telephone line at the same time, and directly use digital signal transmission on the user line by taking advantage of the high frequency and wide bandwidth of digital signals, eliminating the intermediate A/D conversion, breaking through the idle limit rate of analog signal transmission of 56KB/s. DSL technology is mainly divided into two categories: symmetrical and asymmetrical.

xDSLis more suitable for point-to-point connection applications in enterprises, such as file transfer, video conferencing and other tasks where the amount of data sent and received is roughly the same.

ASDLis another broadband access technology developed in recent years. It uses twisted-pair copper wires to provide users with broadband information services with asymmetric rates in two directions.

ADSL transmits one high-speed downstream data, one low-speed upstream data and one analog telephone on a pair of telephone lines at the same time. Each signal occupies different frequency bands using frequency division multiplexing. The low frequency band transmits voice; the middle narrow frequency band transmits upstream channel data and control information; the remaining high frequency bands transmit downstream channel data, images or high-speed data. 20、WLAN interface WLAN (Wireless Local Area Network) is established in a certain local area by using wireless communication technology. It is the product of the combination of computer network and wireless communication technology. It uses wireless multiple access channels as transmission media and provides the functions of wired local area network. WLAN standards: mainly for the physical layer and media access control layer (MAC layer), involving all technical specifications and standards such as the wireless frequency range used and the control interface communication protocol. A, IEEE 802.11: defines the physical layer and MAC layer specifications, operates in the 2.4~2.4835GHz frequency band, with a maximum rate of 2Mb/s. It is a wireless LAN standard originally developed by IEEE. B, IEEE 802.11b: operates at 2.4 to 2.4835GHz frequency band, the maximum rate is 11Mb/s, the transmission distance is 50 to 150 inches. It adopts two operating modes: point-to-point mode and basic mode. In terms of data transmission rate, it can automatically switch between different rates of 11Mb/s, 5.5Mb/s, 2 Mb/s, and 1 Mb/s according to actual conditions. C, IEEE 802.11a: operate in the 5.15~8.825GHz frequency band, with a maximum rate of 54Mb/s/72Mb/s and a transmission distance of 10~100m. D, IEEE 802.11g: Hybrid standard, with the transmission rate of IEEE 802.11a, better security than IEEE 802.11b, using two modulation methods to achieve compatibility with EEE 802.11a and EEE 802.11b. WLAN has two types of networks: peer-to-peer network and infrastructure network. 21. Bluetooth interface The purpose of Bluetooth technology is to enable seamless resource sharing between specific mobile phones, slip-on computers and various portable communication equipment hosts within a short distance. The essence of Bluetooth technology is to establish a universal wireless air interface and an open standard for its control software. Its operating frequency band is universal worldwide. 2.4GHz ISM (Industrial, Scientific, Medical) frequency band, its data transmission rate is 1Mb/s, using time division duplex scheme to achieve full-duplex transmission, its ideal connection range is 10cm~10m. The Bluetooth baseband protocol is a combination of circuit switching and packet switching. Bluetooth technology features: A, short transmission distance, working distance within 10m. B. Frequency hopping spread spectrum technology. C. Time division multiplexing multiple access technology is used to effectively avoid problems such as "collision" and "hidden terminal". D. Network technology. E. Language support. F, error correction technology, which uses the FEC (Forward Error Correction) scheme. The Bluetooth interface consists of three large units: wireless unit, baseband unit, link management and control unit. 22, 1394 interface 1394 as a standard bus, can build a bridge of communication between different industrial equipment, and 63 devices can be connected on one bus. Features of IEEE 1394: A. Supports multiple bus speeds to meet different application requirements. B. Plug and play, supports hot swapping. C. Supports both synchronous and asynchronous transmission modes. D. Supports point-to-point communication mode. IEEE 1394 is a multi-master bus. E. Comply with the ANSI IEEE 1212 control and status register (CSR) standard, define a 64-bit address space, address 63 nodes of 1024 buses, each node can contain 256TB of memory space. F. Support long-distance transmission. G. Support fair arbitration principle to ensure sufficient transmission bandwidth for each transmission method. H. The six-wire cable has a power line that can transmit a DC voltage of 8 to 40V. The IEEE 1394 protocol stack consists of three layers: the physical layer, the link layer, and the transaction layer, with the exception of a management layer. The physical layer and the link layer are composed of hardware, while the transaction layer is mainly implemented by software. A. The physical layer provides IEEEThe electrical and mechanical interface of 1394 is to reassemble the byte stream and send it to the destination node. B. The link layer provides data services confirmed by the transaction layer, including addressing, data framing and data verification. C. The transaction layer provides services for applications. D. The management layer defines all protocols, services and processes used by a management node. 23. Power interface There are three types of DC-DC converters: A. Linear regulator: produces a voltage lower than the input voltage. B. Switching regulator: can increase the voltage, decrease the voltage or invert the input voltage. C. Charge pump: can increase, decrease or invert the input voltage, but has limited current driving capability. No transformer conversion process is 100% efficient. The regulator itself also uses current (quiescent current), which comes from the input current. The larger the quiescent current, the greater the power consumption of the regulator. Linear regulator inputs and outputs are filtered using decoupling capacitors. In addition to helping to smooth the voltage, the capacitor also helps to remove instantaneous short-term pulse waveform interference in the power supply. The square relationship between voltage and power consumption means that the ideal and efficient method is to execute code at a lower clock rate that requires a lower voltage, rather than executing code at the highest clock rate and then going to idle sleep. The power supply is usually considered as the "heart" of the whole system. The energy saving potential of most electronic equipment lies in the power supply system, and the research and development of new switching power supplies is one of the main measures for energy saving. Design technology to reduce power consumption: A. Use low-power devices, such as CMOS circuit chips. B. Use highly integrated special devices, and the selection of external devices should also support low-power design as much as possible. C. Dynamically adjust the processor's clock frequency and voltage, and use low-frequency devices as much as possible when allowed. D. Use the "power saving" working mode. E. Reasonably handle the spare pins of the device: a. When the output of most digital circuits outputs a low level, its power consumption is much greater than that when it outputs a high level. When designing, you should pay attention to controlling the output time of the low level, and keep it in a high level output state when idle. b. The inputs of redundant NOT gates and NAND gates should be connected to a low level, and the inputs of redundant AND gates and OR gates should be connected to a high level. For devices with chip select signals, do not directly ground the chip select pin of c, ROM or RAM and other devices with chip select signals to avoid long F of the device, implement power management, design power control circuit of external devices, and control the power supply of power-consuming large power consumers.Due to the power consumption when outputting high level, attention should be paid to controlling the output time of low level during design, so that it can be in high level output state when idle. The input of redundant NOT gate and NAND gate should be connected to low level, and the input of redundant AND gate and OR gate should be connected to high level. For devices with chip select signals, do not directly ground the chip select pin of c, ROM or RAM and other devices with chip select signals to avoid long F of the device, implement power management, design power control circuit of external devices, and control the power supply of power-consuming large power consumers.Due to the power consumption when outputting high level, attention should be paid to controlling the output time of low level during design, so that it can be in high level output state when idle. The input of redundant NOT gate and NAND gate should be connected to low level, and the input of redundant AND gate and OR gate should be connected to high level. For devices with chip select signals, do not directly ground the chip select pin of c, ROM or RAM and other devices with chip select signals to avoid long F of the device, implement power management, design power control circuit of external devices, and control the power supply of power-consuming large power consumers.

天行漫步

Very good summary