DSP28335 epwm usage

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DSP28335 epwm usage [Copy link]

PWM1,2,3 A,B,C 6 channels initialization #include "pwm.h" //PRD: automatic reload value //CMPA: channel A comparison value //CMPB: channel B comparison value void InitEPwm123(int16 PRD) { InitEPwmGpio(); //Initialize EPWM1, 2, 3 GPIO Epwm1_Init(PRD); Epwm2_Init(PRD); Epwm3_Init(PRD); } //Set EPWM1 module void Epwm1_Init(int16 PRD) { EPwm1Regs.TBPRD = PRD ; //Set period EPwm1Regs.CMPA.half.CMPA = 0; //Set duty cycle EPwm1Regs.CMPB = 0; // Setup TBCLK EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //Increase mode//EPwm1Regs.TBCTL.bit.CTRMODE =TB_COUNT_UPDOWN; //Increase/decrease mode EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; // Disable phase loading EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; // EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 EPwm1Regs.TBCTR = 0x0000; // Clear counter EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; // TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV) // Setup shadow register load on ZERO EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; Incremental mode action EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM1A on Zero EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM1A on event A, up count EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET; // Set PWM1B on Zero EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Clear PWM1B on event B, up count } void Epwm2_Init(int16 PRD) { EPwm2Regs.TBPRD = PRD; //Set the period EPwm2Regs.CMPA.half.CMPA = 0; //Set the duty cycle EPwm2Regs.CMPB = 0; // Setup TBCLK EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;//; // Count up EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW; // Disable phase loading EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; // EPwm2Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 EPwm2Regs.TBCTR = 0x0000; // Clear counter EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; // TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV) // Setup shadow register load on ZERO EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; on Zero EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM1A on event A, up count EPwm2Regs.AQCTLB.bit.ZRO = AQ_SET; // Set PWM1B on Zero EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Clear PWM1B on event B, up count } void Epwm3_Init(int16 PRD) { EPwm3Regs.TBPRD = PRD ; //Set period EPwm3Regs.CMPA.half.CMPA = 0; //Set duty cycle EPwm3Regs.CMPB = 0; // Setup TBCLK EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;//; // Count up
EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE;    // Disable phase loading
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;    // Disable phase loading
    EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;    //
EPwm3Regs.TBPHS.half.TBPHS = 0x0000;       // Phase is 0
EPwm3Regs.TBCTR = 0x0000;                  // Clear counter
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;   // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;      // TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)


// Setup shadow register load on ZERO
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;


    // Set actions
EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET;            // Set PWM1A on Zero
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR;          // Clear PWM1A on event A, up count
    EPwm3Regs.AQCTLB.bit.ZRO = AQ_SET;            // Set PWM1B on Zero
EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR;          // Clear PWM1B on event B, up count

}

头文件

#ifndef PWM_H_
#define PWM_H_
#include "main.h"
#if (CPU_FRQ_150MHZ)
  #define CPU_CLK   150e6
#endif
#if (CPU_FRQ_100MHZ)
  #define CPU_CLK   100e6
#endif
#define PWM_FREQ   10e3                // 10KHZ   If diff freq. desired, change freq here.
//#define SP        CPU_CLK/(2*PWM_CLK)   //上下计数模式
#define SP        ( (CPU_CLK/PWM_FREQ)-1 )     //向上计数模式的自动重装值   10Khz的PWM波

#define SP_UPDOWN         (CPU_CLK/(2*PWM_FREQ))    //向上计数模式的自动重装值

// Configure the period for each timer
#define EPWM1_TIMER_TBPRD  SP  // Period register
#define EPWM1_MAX_CMPA     SP-10
#define EPWM1_MIN_CMPA       10
#define EPWM1_MAX_CMPB     SP-10
#define EPWM1_MIN_CMPB       10

#define EPWM2_TIMER_TBPRD   SP // Period register
#define EPWM2_MAX_CMPA     SP-10
#define EPWM2_MIN_CMPA       10
#define EPWM2_MAX_CMPB     SP-10
#define EPWM2_MIN_CMPB       10

#define EPWM3_TIMER_TBPRD  SP  // Period register
#define EPWM3_MAX_CMPA     SP-10
#define EPWM3_MIN_CMPA       10
#define EPWM3_MAX_CMPB     SP-10
#define EPWM3_MIN_CMPB     10

#define Set_EPWM1A(Val)   EPwm1Regs.CMPA.half.CMPA = Val  //设置占空比
#define Set_EPWM1B(Val)   EPwm1Regs.CMPB = Val  //设置占空比
#define Set_EPWM2A(Val)   EPwm2Regs.CMPA.half.CMPA = Val  //设置占空比
#define Set_EPWM2B(Val)   EPwm2Regs.CMPB = Val  //设置占空比
#define Set_EPWM3A(Val)   EPwm3Regs.CMPA.half.CMPA = Val  //设置占空比
#define Set_EPWM3B(Val)   EPwm3Regs.CMPB = Val  //设置占空比

void InitEPwm123(int16 PRD);
void Epwm1_Init(int16 PRD);
void Epwm2_Init(int16 PRD);
void Epwm3_Init(int16 PRD);

#endif /* PWM_H_ */

main函数中要到的函数

InitEPwm123(SP); //SP macro is defined as the auto-reload value, adjusted according to different PWM wave frequencies Set_EPWM1A(SP/4); //Set to different duty cycles Set_EPWM1B(SP*7/8); Set_EPWM2A(SP/5); Set_EPWM2B(SP/4); Set_EPWM3A(SP/3); Set_EPWM3B(SP/2);