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Basys3 Oscilloscope Experiment Design Based on FPGA Vivado 17.2 [Copy link]


Based on FPGA vivado 17.2 Basys3 oscilloscope experiment design attachment: Basys3_workshop_lab4.zip (4.69 MB, downloads: 56) This content is originally created by EEWORLD forum user 大辉哥0614. If you need to reprint or use it for commercial purposes, you must obtain the author's consent and indicate the source I. Experimental purpose 1) Master the Vivado engineering design process based on adding files and IP 2) Master the Vivado engineering design process based on Tcl 3) Learn the basic composition structure of the oscilloscope II. Experimental principle introduction Digital storage oscilloscope can sample, store and display analog signals. This system builds a simple digital storage oscilloscope on DIGILENT Basys3. The simplified block diagram is as follows: Principle: First, the AD module samples the analog signal, and the trigger circuit determines the trigger condition (for example: rising edge trigger) according to the sampled signal. After the trigger condition is met, a certain number of points (640 points in this system) are continuously sampled and stored in RAM. The peak-to-peak value and frequency calculation module calculates the waveform data stored in RAM to obtain the frequency and peak-to-peak value of the waveform; the VGA module displays the waveform and displays the calculated peak-to-peak value and frequency values. This experiment samples and stores the external voltage signal by calling the ADC module in the DIGILENT Basys3 on-board chip, and displays the waveform on the VGA display. Before powering on the DIGILENT Basys3, you need to connect the DIGILENT Basys3 to the VGA in advance and prepare a signal generator. 3. Experimental steps (based on adding files and IP) 1. Create a new project 1) Double-click the desktop icon to open Vivado 2017.2, or select Start>All Programs>Xilinx Design Tools>Vivado 2017.2>Vivado 2017.2 2) Click 'Create Project', or click File>New Project to create a project file 3) Name the new project 'lab4', select the project save path, check 'Create project subdirectory', create a new project folder, and click Next to continue 4) Choose to create a new RTL project, check Do not specify sources at this time (do not specify to add source files), and do not add source files first. Click Next to continue 5) Select the target FPGA device: xc7a35tcpg236-1 or Basys3. 6) Finally, in the new project summary, check whether the project creation is correct. If there is no problem, click Finish to complete the creation of the new project. 2. Add the designed IP and source files. After the project is established, we will copy the IP folder (IP_Catalog) required for Experiment 4 and the HDL (Verilog) files needed for the experiment to the root directory of the created project folder: The source files are located in Basys3_workshop\sources\lab4\Src\HDL_source. After the copying is completed, it will be as shown in the figure below: 1) Expand PROJECT MANAGER in the Flow Navigator on the left side of the Vivado interface and select 'Settings' 2) In the pop-up window, expand IP in Project Settings on the left, select 'Repository', and click Add IP on the right. 3) Select the IP folder copied to the root directory of the project folder 4) Click OK to complete the addition. 5) Add IP to the project 5.1 Expand PROJECT MANAGER in Flow Navigator and select IP Catalog 5.2 Search for 'clocking' in the search box of the IP Catalog window on the right and double-click 'Clocking Wizard' to start configuring the IP 5.3 Configure IP 5.3.1 Change the name of the IP from 'clk_wiz_0' to 'clock' 5.3.2 Select 'Output Clocks' and set 7 output clocks (100MHz, 25MHz, 12.5MHz, 25MHz, 50MHz, 75MHz, 100MHz) 5.3.3 Uncheck the 'reset' and 'locked' options in Enable Optional I/O for MMCM/PLL 5.3.4 Vivado will create a new folder to save the configured IP, click OK to continue 5.3.5 The Generate Output Products window pops up, select 'Global' in Synthesis Options, and click 'Generate' to continue. 5.4 Similarly, add the three IPs of debounce, vga and xadc in the IP Catalog window in turn, use the default IP settings, no additional configuration is required, and Generate Output Products. After completion, the Sources pane should look like the following figure: 6) Add HDL files to the project 6.1 Expand PROJECT MANAGER in Flow Navigator and select Add Sources 6.2 Select 'Add or create design sources' in the wizard window and click Next to continue 6.3 Select 'Add Files' in the Add or Create Design Sources page 6.4 Find the lab4 root directory and select to add all 9 Verilog files. 6.5 Check 'Copy sources into project' and click Finish to complete the addition. 6.6 After completion, the Sources pane should look like the following figure: 7) Add physical constraint (XDC) file 7.1 Expand PROJECT MANAGER in Flow Navigator and select Add Sources 7.2 Select 'Add or create constraints' in the wizard window and click Next to continue 7.3 Select 'Add Files' in the Add or Create Design Sources page 7.4 Find the constraint file path Basys3_workshop\sources\lab4\Src\Constraint, select and add the 'oscilloscope.xdc' file 7.5 Check 'Copy sources into project' and click Finish to complete the addition. 3.Synthesis, implementation, and bitstream file generation 1) In the Flow Navigator on the left, click 'Run Synthesis', 'Run Implementation', and 'Generate Bitstream' in sequence to perform synthesis, implementation, and generate bitstream file operations. Alternatively, you can directly click 'Generate Bitstream', and the Vivado tool will prompt that there is no implemented result. Click 'Yes', and the Vivado tool will perform synthesis, implementation, and generate bitstream files in sequence. 2) After completion, select 'Open Hardware Manager' to open the hardware manager. 3) Connect the Basys3 development board, click 'Open target', and select 'Auto connect'. 4) After the connection is complete, click 'Program device'. 5) Check the selected bit file in the pop-up box, and then click Program to download. IV. Experimental steps (based on Tcl) 1. Run Tcl and create a new project 1) Open Vivado 2017.2, and enter the command in the Tcl command box at the bottom of the interface 2) Use the 'cd' command to enter the path where the Oscilloscope.tcl file is located. Reference path: C:\Basys3_workshop\sources\lab4\Src\Tcl, enter in the Tcl command box: cd C:/Basys3_workshop/sources/lab4/Src/Tcl (Note: Vivado uses '/') 3) In the Tcl command box, enter the command: source ./ Oscilloscope.tcl. After input, press Enter to run Tcl 4) Wait for Tcl to synthesize, implement, and generate bitstream files 5) In Flow Navigator, expand PROGRAM AND DEBUG, click Open Hardware Manager, and click Open target>Auto Connect to connect to Basys3 6) Click Program device, select the generated bitstream file to start downloading V. Basys3 Experimental Verification After the bitstream file is downloaded, you can connect the signal generator probe to the P pole of Basys3's JXADC, and connect the N pole of JXADC to the ground of the signal generator. In this experiment, the measurable voltage range of the simple oscilloscope is 0-1V, and the frequency is below 4KHz. The waveform can be observed on the VGA. If the waveform display is dense, you need to change the sampling clock. Press the BTNC button on the Basys3 development board to change the sampling clock to change the density of the waveform display. 1. Based on Analog Discovery2 According to the connection method shown in the figure below, connect the output leads W1 (yellow) and W2 (yellow-white) of the waveform generator of Analog Discovery2 to pin1 and pin7 of Basys3's JXADC. 1) Open WaveForms software and connect Analog Discovery2 device 2) Select 'Wavegen' in the function selection bar on the left to use the waveform generator. 3) According to the input standard of the oscilloscope design of this experiment, set the waveform amplitude to 400mV, the DC offset to 500mV, and the input frequency can be selected between 100H~5kHz 4) Click 'Run All' in the upper left corner to start running. Press the BTNC button on the Basys3 development board to adjust the sampling frequency and observe the output results on the VGA monitor 2. Based on OpenScope According to the connection method shown in the figure below, connect the output lead W1 (yellow) of the waveform generator of OpenScope to pin1 of JXADC of Basys3. 1) Open Digilent Agent 2) On the right side of the Windows toolbar, right-click the Digilent Agent icon and select 'Launch WaveForms Live' to open WaveForms Live in the browser. 3) Select the device you added in Experiment 2 and click Connect to it 4) Find and expand Wavegen on the right and configure it according to the following parameters: Select sine wave Frequency: 2 kHz Amplitude: 1 Vpp DC Offset: 1.4 V 5) Click the switch button in the upper right corner to turn on the waveform generator. 6) Observe the output results on the VGA monitor. You can use the BTNC button on the Basys3 development board to adjust the sampling frequency.Based on Analog Discovery2 According to the connection method in the figure below, connect the output pins W1 (yellow) and W2 (yellow-white) of the waveform generator of Analog Discovery2 to pin1 and pin7 of JXADC of Basys3. 1) Open WaveForms software and connect the Analog Discovery2 device 2) Select 'Wavegen' in the function selection bar on the left to use the waveform generator. 3) According to the input standard of the oscilloscope design of this experiment, set the waveform amplitude to 400mV, the DC offset to 500mV, and the input frequency can be selected between 100H~5kHz 4) Click 'Run All' in the upper left corner to start running. Press the BTNC button on the Basys3 development board to adjust the sampling frequency and observe the output results on the VGA monitor [attach]335913 [/attach] 2. Based on OpenScope According to the connection method in the figure below, connect the output lead W1 (yellow) of the waveform generator of OpenScope to pin1 of JXADC of Basys3. 1) Open Digilent Agent 2) On the right side of the Windows toolbar, right-click the Digilent Agent icon and select 'Launch WaveForms Live' to open WaveForms Live in the browser. 3) Select the device that has been added in Experiment 2 and click to connect the device [attach]335915 [/attach] 4) Find and expand Wavegen on the right and configure it according to the following parameters: Select sine wave Frequency: 2 kHz Amplitude: 1 Vpp DC Offset: 1.4 V 5) Click the switch button in the upper right corner to turn on the waveform generator. 6) Observe the output results on the VGA monitor and use the BTNC button on the Basys3 development board to adjust the sampling frequency.Based on Analog Discovery2 According to the connection method in the figure below, connect the output pins W1 (yellow) and W2 (yellow-white) of the waveform generator of Analog Discovery2 to pin1 and pin7 of JXADC of Basys3. 1) Open WaveForms software and connect the Analog Discovery2 device 2) Select 'Wavegen' in the function selection bar on the left to use the waveform generator. 3) According to the input standard of the oscilloscope design of this experiment, set the waveform amplitude to 400mV, the DC offset to 500mV, and the input frequency can be selected between 100H~5kHz 4) Click 'Run All' in the upper left corner to start running. Press the BTNC button on the Basys3 development board to adjust the sampling frequency and observe the output results on the VGA monitor [attach]335913 [/attach] 2. Based on OpenScope According to the connection method in the figure below, connect the output lead W1 (yellow) of the waveform generator of OpenScope to pin1 of JXADC of Basys3. 1) Open Digilent Agent 2) On the right side of the Windows toolbar, right-click the Digilent Agent icon and select 'Launch WaveForms Live' to open WaveForms Live in the browser. 3) Select the device that has been added in Experiment 2 and click to connect the device [attach]335915 [/attach] 4) Find and expand Wavegen on the right and configure it according to the following parameters: Select sine wave Frequency: 2 kHz Amplitude: 1 Vpp DC Offset: 1.4 V 5) Click the switch button in the upper right corner to turn on the waveform generator. 6) Observe the output results on the VGA monitor and use the BTNC button on the Basys3 development board to adjust the sampling frequency.


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The landlord is terrible  Details Published on 2017-12-24 20:08
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Basys3 Oscilloscope Experiment Design Based on FPGA Vivado 17.2
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Thanks for sharing, happy holidays
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Thank you for sharing, thank you for your hard work
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The landlord is terrible
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lclhitwh posted on 2017-12-22 21:14 Thanks for sharing, happy holidays
Haha, thanks, I haven't been to the forum recently
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Haha, the word is wrong
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lclhitwh posted on 2017-12-22 21:14 Thanks for sharing, happy holidays
Haha, thanks, I haven't been to the forum recently
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Personal signature想学FGPA,至芯科技 昭哥带你学,联系方式:15201114008
 
 
 

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Anyone who wants to learn FPGA can come here. Classes are offered simultaneously in Beijing, Xi'an, and Wuhan. Free hotel accommodation for 10 days is provided. Hahahaha
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Anyone who wants to learn FPGA can come here. Courses are offered simultaneously in Beijing, Xi'an, and Wuhan. Free hotel accommodation for 10 days is provided. Hahahaha
This post is from FPGA/CPLD
Personal signature想学FGPA,至芯科技 昭哥带你学,联系方式:15201114008
 
 
 

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