Talk about MSP430F149 internal resources - timer

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Talk about MSP430F149 internal resources - timer [Copy link]

Timer is an important part that is often used in MSP430 application system. (I) The functions that can be realized are: 1. Timing causes interruption 2. Delay 3. Provide serial port bit rate 4. Signal generation 5. Signal detection (in capture mode) 6. Frequency measurement 7. Pulse width measurement (II) Generally speaking, the timing signal required by MSP430 can be realized by software and hardware; 1. Software timing: Design a delay program to save hardware, and the required time is easy to adjust, but the CPU is occupied during the execution of the program, which reduces the CPU utilization rate; 2. Hardware timing: Use a special timing device as the main implementation device to generate accurate time delay under simple software control; set the time constant through instructions, and start the timer by instructions. (III) Timing resources of MSP430F149: 1. WDT-Watchdog timer During normal operation, a WDT overflow will generate a system reset. If the WDT timing time is slightly longer than the time required for the program to execute once, and the program contains instructions to clear the WDT, the EDT will be re-counted. Then when the program runs normally, it will be cleared before the WDT time arrives, and no system reset will occur; if the program runs away, there will be no instruction to clear it when the WDT time arrives, and a WDT overflow will occur, causing a system reset and the program to restart execution, thus avoiding unpredictable errors caused by program execution errors. WDT register resources: a. WDTCNT----counting unit, which is a 16-bit up counter; b. WDTCTL----control register, which consists of two parts. The upper 8 bits are used as passwords, and the lower 8 bits are used to control the WDT process. To write the control command for the WDT operation, you must first correctly write the high-byte watchdog password, which is 5AH. If the password is written incorrectly, it will cause a system reset. Functions that can be achieved through the lower 8 bits of the control register IS0, IS1-----Select the timing output of the watchdog timer SSEL-----Select the clock source of WDT CNTCL---- Clear WDTCNT when this position is 1 TMSEL----Working mode selection 0---Watchdog mode, 1---Timer mode NMI-----Select the RST/NMI pin function, which is reset after PUC 0---Reset terminal, 1----Edge-triggered non-maskable interrupt input NMIES---Select the edge trigger mode of the interrupt 0---Rising edge trigger, 1---Falling edge trigger HOLD-----Stop the watchdog timer and reduce power consumption 0---WDT function activation, 1---WDT stops working. WDT uses two bits of the SFR address: interrupt flag bit WDTIFG---located at IFG1.0, the initial state is reset; interrupt enable bit WDTIE---located at IE1.0, the initial state is reset. Watchdog timer: The interrupt triggered in watchdog mode is a non-maskable interrupt. The interrupt triggered in timer mode is a maskable interrupt. Through WDTCTL, the timing time, working mode, interrupt mode and low power mode of WDT can be selected. Watchdog shutdown statement: WDTCTL = WDTPW + WDTHOLD; //WDTPW ---- password, fixed value 0x5A00 //WDTHOLD ---- 0x0080, HOLD position. The WDT function activation timing cycle is 32ms: WDTCTL = WDT_MDLY_32; //Where: WDT_MDLY_32 = WDTPW+WDTTMSEL+WDTCNTCL //WDTTMSEL = 0x0004, TMSEL is set to 1, select the timer mode //WDTCNTCL = 0x0008, CNTCL is set to 1, clear WDTCNT 2. Timer_A----Timer A consists of a 16-bit timer and multiple comparator/capture channels. Each comparison/capture channel is controlled separately with the timing function of the 16-bit timer as the core. Features of Timer_A: a. It can not only capture the time when an external event occurs, but also lock the high and low levels when it occurs b. 4 counting function options c. 8 output mode options d. Serial communication can be realized e. The time constant cannot be overloaded Timer_A consists of the following three parts a. Counter part: There are 4 options for the input clock source, and 1, 2, 4, and 8 divisions can be selected; b. Capture/Comparator: The capture and comparator work completely independently and are used to capture the time or time interval of an event. c. Output unit: It has 8 optional outputs to generate signals required by the user. Register resources of Timer_A: a. TAR------16-bit counter b. TACTL----control register SSEL1, SSEL0-----used to select the clock source of the timer ID1, ID0-----used to select the frequency division MC1,MC0-----Counting mode control bit CLR---------Timer clear bit TAIE--------Timer interrupt enable bit TAIFG-------Timer overflow flag bit Incremental counting mode: When the timer counts from 0FFFFH to 0, set the continuous counting mode: When the timer counts from 0FFFFH to 0, set the increment and decremental counting mode, when the timer decreases from 1 to 0, set c, CCRx-----Capture/compare register When the capture condition is met, the hardware automatically writes the counter TAR data into this register. If you want to measure a certain pulse length, you can define both the rising edge and the falling edge to capture. At the rising edge, capture one timer data, and at the falling edge, capture another timer data. Then the difference between these two timing data is the pulse width. d. CCTLx---Capture/compare control register CM1, CM0--------Select capture mode CCIS1, CCIS0----Used to define the input source that provides capture events in capture mode SCS------------Select whether the capture signal is synchronous or asynchronous COV------------Capture overflow flag CCIEx----------Capture/compare module interrupt enable bit CCIFGx---------Capture register interrupt flag CAP-----------Select capture mode or comparison mode 0---Comparison mode, 1----Capture mode OUTMODx-------Select output mode OUT-----------Output signal 0---Output low level, 1---Output high level CCIx----------Capture compare module input signal SCCIx---------Compare equal signal EQUx Latch the selected capture/compare input signal CCIx, and then it can be read by SCCIx In capture mode, the input signal selected by CCIS0, CCIS1 can be read through this bit. e. TAIV-------------Interrupt vector register Timer_A interrupt can be caused by counter overflow or from capture/comparator. Each capture/comparator can be independently programmed to generate interrupts by external signals. The external signal can be a rising edge, a falling edge, or both. The Timer_A module uses two interrupt vectors, one is assigned to capture/comparator 0 alone, and the other is used as a shared interrupt vector for the timer and other capture/comparators. The capture/compare register CCR0 interrupt vector has the highest priority because it can be used to define the cycle of the up-count and up/down count modes and requires the fastest service. CCR1--CCRx shares an interrupt vector with the timer and is a multi-source interrupt. The corresponding interrupt flags CCIFG1-- CCIFGx and TAIFG1 are automatically reset after reading the interrupt vector word TAIV; if the TAIV register is not accessed, it will not be automatically reset and needs to be cleared by the user software. If the corresponding interrupt allows reset (interrupt is not allowed), no interrupt request will be generated, but the interrupt flag still exists and needs to be cleared by software. If there is a Timer_A interrupt flag, TAIV is the corresponding data. The data is added to the value of PC to enable the system to automatically enter the corresponding interrupt service routine. Set timer A, select MCLK, clear TAR, and enable timer overflow interrupt TACTL = TASSEL1 + TACLR + TAIE; //TASSEL1 = 0x0200, SSEL is set, and MCLK is selected //TACLR = 0x0004, CLR is set, TAR is cleared //TAIE = 0x0002, IE is set, and timer interrupt is enabled 3. Timer_B----Timer BCCIS0----used to define the input source that provides capture events in capture mode SCS------------Select whether the capture signal is synchronous or asynchronous COV------------Capture overflow flag CCIEx----------Capture/compare module interrupt enable bit CCIFGx---------Capture register interrupt flag CAP-----------Select capture mode or comparison mode 0---Comparison mode, 1----Capture mode OUTMODx-------Select output mode OUT-----------Output signal 0---Output low level, 1---Output high level CCIx----------Capture compare module input signal SCCIx---------Compare equal signal EQUx Latch the selected capture/compare input signal CCIx, and then it can be read by SCCIx In capture mode, the input signal selected by CCIS0, CCIS1 can be read through this bit. e. TAIV-------------Interrupt vector register Timer_A interrupt can be caused by counter overflow or from capture/comparator. Each capture/comparator can be independently programmed to generate interrupts by external signals. The external signal can be a rising edge, a falling edge, or both. The Timer_A module uses two interrupt vectors, one is assigned to capture/comparator 0 alone, and the other is used as a shared interrupt vector for the timer and other capture/comparators. The capture/compare register CCR0 interrupt vector has the highest priority because it can be used to define the cycle of the up-count and up/down count modes and requires the fastest service. CCR1--CCRx shares an interrupt vector with the timer and is a multi-source interrupt. The corresponding interrupt flags CCIFG1-- CCIFGx and TAIFG1 are automatically reset after reading the interrupt vector word TAIV; if the TAIV register is not accessed, it will not be automatically reset and needs to be cleared by the user software. If the corresponding interrupt allows reset (interrupt is not allowed), no interrupt request will be generated, but the interrupt flag still exists and needs to be cleared by software. If there is a Timer_A interrupt flag, TAIV is the corresponding data. The data is added to the value of PC to enable the system to automatically enter the corresponding interrupt service routine. Set timer A, select MCLK, clear TAR, and enable timer overflow interrupt TACTL = TASSEL1 + TACLR + TAIE; //TASSEL1 = 0x0200, SSEL is set, and MCLK is selected //TACLR = 0x0004, CLR is set, TAR is cleared //TAIE = 0x0002, IE is set, and timer interrupt is enabled 3. Timer_B----Timer BCCIS0----used to define the input source that provides capture events in capture mode SCS------------Select whether the capture signal is synchronous or asynchronous COV------------Capture overflow flag CCIEx----------Capture/compare module interrupt enable bit CCIFGx---------Capture register interrupt flag CAP-----------Select capture mode or comparison mode 0---Comparison mode, 1----Capture mode OUTMODx-------Select output mode OUT-----------Output signal 0---Output low level, 1---Output high level CCIx----------Capture compare module input signal SCCIx---------Compare equal signal EQUx Latch the selected capture/compare input signal CCIx, and then it can be read by SCCIx In capture mode, the input signal selected by CCIS0, CCIS1 can be read through this bit. e. TAIV-------------Interrupt vector register Timer_A interrupt can be caused by counter overflow or from capture/comparator. Each capture/comparator can be independently programmed to generate interrupts by external signals. The external signal can be a rising edge, a falling edge, or both. The Timer_A module uses two interrupt vectors, one is assigned to capture/comparator 0 alone, and the other is used as a shared interrupt vector for the timer and other capture/comparators. The capture/compare register CCR0 interrupt vector has the highest priority because it can be used to define the cycle of the up-count and up/down count modes and requires the fastest service. CCR1--CCRx shares an interrupt vector with the timer and is a multi-source interrupt. The corresponding interrupt flags CCIFG1-- CCIFGx and TAIFG1 are automatically reset after reading the interrupt vector word TAIV; if the TAIV register is not accessed, it will not be automatically reset and needs to be cleared by the user software. If the corresponding interrupt allows reset (interrupt is not allowed), no interrupt request will be generated, but the interrupt flag still exists and needs to be cleared by software. If there is a Timer_A interrupt flag, TAIV is the corresponding data. The data is added to the value of PC to enable the system to automatically enter the corresponding interrupt service routine. Set timer A, select MCLK, clear TAR, and enable timer overflow interrupt TACTL = TASSEL1 + TACLR + TAIE; //TASSEL1 = 0x0200, SSEL is set, and MCLK is selected //TACLR = 0x0004, CLR is set, TAR is cleared //TAIE = 0x0002, IE is set, and timer interrupt is enabled 3. Timer_B----Timer B